EP80579 Datasheet, PDF (1231/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
34.2.2.34 Offset E0h: PMCS – Power Management Control and Status Register
For an overview of the power management capability of AIOC devices, see Section
35.5, “Power Management of AIOC Devices” on page 1236.
Table 34-36. Offset E0h: PMCS: Power Management Control and Status Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:4:0
Offset Start: E0h
Offset End: E1h
Size: 16 bit
Default: 0008h
Power Well: Core
Bit Range Bit Acronym
Bit Description
15
14 : 13
12 : 09
08
07 : 04
03
02
01 : 00
PME Status - This bit is sticky for device 0 which is on
PME_STATUS suspend well, but not for the other 2 which aren’t on a
power well.
DATA_SCALE Data Scale
DATA_SEL Data Select
PME_EN
PME Enable - This bit is sticky for device 0 which is on
suspend well, but not for the other 2 which aren’t on a
power well.
Reserved Reserved
NSR
No Soft Reset
Reserved Reserved
PS
Power State
Sticky
Bit Reset
Value
Bit Access
0h
RO
00b
RO
0000b
RO
0h
RO
0000b
RO
1
RO
0h
RO
00b
RW
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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