EP80579 Datasheet, PDF (645/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 16-290.Legoverride - Gray code
CSR value for
static impedance
control (binary)
Desired value for
impedance control
(Decimal)
1100
8
0100
7
0101
6
0111
5
0110
4
0010
3
00011
2
0001
1
0000
0
:
Table 16-291.Offset 268h: DDRIOMC2 - DDRIO Mode Control Register 2
Description: DDRIOMC2: DDRIO Mode Control Register 2
View: PCI
BAR: SMRBASE
Bus:Device:Function: 0:0:0
Offset Start: 268h
Offset End: 26Bh
Size: 32 bit
Default: 039E6000h
Power Well: Core
Bit Range
31 :28
27 26
25 16
15 15
14 :12
11 :00
Bit Acronym
Bit Description
Sticky
Bit Reset
Value
Bit Access
Reserved Reserved
N
0000b
RO
PHSEL
Core phase to Command/Address relationship.
Y
00b
RW
Digital Impedance Control for RCOMP of DDR pads. See
Legoverride table above.
LEGOVERRIDE
Do not use the Default setting Please refer to Section
11.4.6, “RCOMP” for more details.
Y 1110011110b
RW
This bit clears the DDRIO Receive FIFO read and write
pointers. The write pointer of this FIFO is generated by the
DDRIO logic based on DQS while the read pointer is
generated by the memory controller.
The DDRIO receive FIPO read/write pointers need to be
FIFOWPTRCLR
cleared after DCAL or Mbist operations are completed and
before issuing any functional DRAM R/W operations.
N
0b
RW
Unlike SDRC.DDRRFRS this register will reset only the
read/write pointers of the DDRIO receive FIFO. It will not
reset the DLL’s. Please see Section 16.1.1.45, “Offset 88h:
SDRC – DDR SDRAM Secondary Control Register” for more
details.
MASTCNTL Coarse delay of DQS Master DLL
Y
110b
RW
Reserved Reserved
N
000000000000
b
RO
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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