EP80579 Datasheet, PDF (987/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
26.2.1.14 Offset 3Ch: ILINE - Interrupt Line Register
Table 26-16. Offset 3Ch: ILINE - Interrupt Line Register
Description: Lockable: D3-to-D0
View: PCI
BAR: Configuration
Bus:Device:Function: 0:29:7
Offset Start: 3Ch
Offset End: 3Ch
Size: 8 bit
Default: 00h
Power Well: Core
Bit Range
07 :00
Bit Acronym
Bit Description
ILINE
Interrupt line: This data is not used. It is used as a
scratchpad register to communicate to software the
interrupt line that the interrupt pin is connected to.
Sticky
Bit Reset
Value
Bit Access
00h
RW
26.2.1.15 Offset 3Dh: IPIN - Interrupt Pin Register
Table 26-17. Offset 3Dh: IPIN - Interrupt Pin Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:29:7
Offset Start: 3Dh
Offset End:3D 3Dh
Size: 8 bit
Default: Variable
Power Well: Core
Bit Range
07 :00
Bit Acronym
Bit Description
Sticky
IPIN
Interrupt pin: Bits 03:00 reflect the value of D29IP.EIP in
configuration space. Bits 07:04 are hardwired to 0000b.
Bit Reset
Value
Variable
Bit Access
RO
26.2.1.16 Offset 50h: PM_CID - PCI Power Management Capability ID Register
Table 26-18. Offset 50h: PM_CID - PCI Power Management Capability ID Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:29:7
Offset Start: 50h
Offset End: 50h
Size: 8 bit
Default: 01h
Power Well: Core
Bit Range
07 :00
Bit Acronym
Bit Description
PM_CID
A value of 01h indicates that this is a PCI Power
Management capabilities field.
Sticky
Bit Reset
Value
Bit Access
01h
RO
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
987