EP80579 Datasheet, PDF (136/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
4.3.2.1
configuration in the MSI and Signal Target capability records in the PCI configuration
header. These records allow the signal bridge to determine how to handle an inbound
signal from a device.
All side band signals from a given source are collected at the signal bridge. For
example, a source may provide interrupt lines and error condition lines that cause the
EP80579 to send a signal when any one is asserted. Sets of side band signals are then
associated with each AIOC PCI device that can signal. When a given side band signal
asserts, the signal bridge looks up the MSI and Signal Target capability records in the
PCI configuration header that corresponds to the device. These resources tell the signal
bridge how and where to deliver the outbound signal:
• If the masks in the Signal Target capability record indicate the signal should be
delivered to the IA-32 core, the signal bridge sends an MSI or INTx signal to the IA-
32 core.
— If the PCI configuration header selects MSI messaging, the signal bridge
generates an MSI transaction from the device that generates the signal to the
IA-32 core in accordance with the MSI capability record.
— If the PCI configuration header selects INTx messaging, the signal bridge
generates an INTx transaction to the IA-32 core.
The status register in the Signal Target Capability provides the state of the side-band
signals associated with a given AIOC PCI device to help software disambiguate the
source of the signal.
Targeting the IA-32 core with a Bridged Signal
To remain compatible with existing IA software stacks, EP80579 hardware supports the
PCI MSI and legacy INTx signaling mechanisms into the CMI in response to signals
targeting the IA-32 core.
• MSI enable field selects the signaling mechanism an MSI-capable device uses:
— INTx legacy mode.
— MSI mode.
• MSI capability record specifies how IA system software wants MSI-capable devices
to signal the IA-32 core through a message address and message data register.
• Interrupt pin and line registers specify the interrupt pin and line that the hardware
uses for legacy INTx mode.
• Interrupt disable bit in the command register specifies whether or not the device
generates any signals.
Based on the PCI abstraction, these are per-device fields that are logically associated
with a given device and that all devices that can signal the IA-32 core must implement.
Software is free to mix signal delivery mechanisms at the device level. For example, it
may configure the EP80579 such that the Gigabit Ethernet MACs signal through MSIs
while the remaining AIOC devices signal through INTx.
When device X signals the IA-32 core, it consults the PCI configuration header for
device X to determine how to deliver the signal to IA (i.e., via MSI or INTx). For
signaling via MSI, the header identifies the address and data value in the MSI
transaction. Hardware builds the 32-bit data value for the MSI transaction from the
contents of the PCI MSI Message Data Register, mdr, according to the PCI semantics.
Specifically, the data value sent in the MSI to IA is:
• Bits 31:16 are zero.
• Bits 15:0 are mdr, the value of the PCI MSI Data Register in the PCI configuration
header of the source device¹.
Intel^® EP80579 Integrated Processor Product Line Datasheet
136
August 2009
Order Number: 320066-003US