EP80579 Datasheet, PDF (425/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 16-45. Offset 78h: DRT0 - DRAM Timing Register 0 (Sheet 2 of 7)
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:0:0
Offset Start: 78h
Offset End: 7Bh
Size: 32 bit
Default: 242AD280h
Power Well: Core
Bit Range
Bit Acronym
Bit Description
Sticky
Back To Back Read Turn Around: This field determines
the minimum number of CMDCLK on the DQ bus between
two reads destined to different ranks. The purpose of these
bits is to control the turnaround time on the DQ bus.
The encoding below will be translated by the hardware into
a number of CMDCLK’s that will be inserted between read
write commands.
Bit Reset
Value
Bit Access
28 :26
BTBRTA
Encoding
000
001
010
011
100
101
110
111
Command
Clocks per
Frequency
0
1
2
3
4
5
6
7
N
001b
RW
Back to Back Write-Read turn around: This field
determines the minimum number of CMDCLK on the DQ
bus between Write-Read commands. The purpose of these
3 bits are to control the turnaround time on the DQ bus.
The encoding below will be translated by the hardware into
a number of CMDCLK’s that will be inserted between read
write commands.
Command clocks apart based on the following encoding:
25 :23
BBWRTA
Encoding
000
001
010
011
100
101
110
111
Command
Clocks per
Frequency
0
1
2
3
4
5
6
7
N
000b
RW
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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