EP80579 Datasheet, PDF (803/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
22.0 General Purpose I/O: Bus 0, Device 31, Function 0
22.1
Note:
Overview
• The following GPIO pins are implemented:
Pin direction is related to GPIO mode.
Input Only
: 22 (00:15, 26, 29:31, 40:41)
Output Only : 8 (16:21, 23, 48)
Input/Output : 6 (24:25, 27:28, 33:34).
• GPIO pins [22, 32, 35:39, 42:47, 50:63] do not exist.
• Some of the GPIO pins can be configured to be used for alternate functions. The
alternate function and IRQ mapping of function multiplexed GPIO pins is provided
in Table 22-1.
• GPIO pins [16:21, 23:25, 27:28, 30:31, 33:34, 40] are configured to generate IRQ
interrupt to IO-APIC if ETR3.GPIO_IRQ_STRAP_STS = 1 [strap pulling SIU2_TXD to
Low on the rising edge of PWROK). But BIOS can still change the function of each
of these pins to GPIO mode by programming the individual bits in GPIO_USE_SELx
register.
• Bits in GPIO_USE_SELx register enable GPIO[n] (where n is the bit number) to be
used as a GPIO, rather than for the alternative function. Pin is used as GPIO when
the individual bit in GPIO_USE_SELx register is set, otherwise used as alternative
function. Example: Software sets bit 2 in this register to enable GPIO[2] (instead of
using that signal for PIRQ[E]#).
• If GPIO[n] does not exist, then the bit in GPIO_USE_SELx register is always read as
0 and writes have no effect. Example: Bit 22 in GPIO_USE_SEL1 is not supported
because there is no corresponding GPIO[22].
• GPIO pins [0:1, 6:10, 12:15, 48] do not have an alternative function.
• GPIO pins can not generate IRQ interrupt when ETR3.GPIO_IRQ_STRAP_STS = 0.
• When configured to IRQ mode, the pin direction of the relevant pins are set to
“input” by GPIO logic. ICH6 compatibility is expected when the GPIOs are in GPIO
mode.
• When configured to GPIO mode, the muxing logic presents the inactive state to
alternate mode logic that uses the pin as an input.
• After a full reset (RSMRST#), all multiplexed signals in the resume and core wells
are configured as GPIO rather than their alternative function.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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