EP80579 Datasheet, PDF (487/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 16-93. Offset 88h: DRAM_SCICMD - DRAM SCI Command Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:0:1
Offset Start: 88h
Offset End: 88h
Size: 8 bit
Default: 00h
Power Well: Core
Bit Range
07
06
05 :04
03
02
01
00
Bit Acronym
Bit Description
Sticky
Memory Test Complete SCI Enable: Generate SCI when
Bit 7 of DRAM_FERR or DRAM_NERR is set.
MTC_SCI _{0 = Disable}
N
1 = Enable
Poisoned Write to DRAM SCI Enable: Generate SCI
when Bit 6 of DRAM_FERR or DRAM_NERR is set.
PWD_SCI _{0 = Disable}
N
1 = Enable
Reserved Reserved
N
Error Threshold Detect SCI Enable: Generate SCI when
Bit 3 of DRAM_FERR or DRAM_NERR is set.
ETD_SCI _{0 = Disable}
N
1 = Enable
Scrubber Data Error SCI Enable: Generate SCI when Bit
2 of DRAM_FERR or DRAM_NERR is set.
SDE_SCI _{0 = Disable}
N
1 = Enable
Uncorrectable Read Memory Error SCI Enable:
Generate SCI when Bit 1 of DRAM_FERR or DRAM_NERR is
URME_SCI ^set.
N
0 = Disable
1 = Enable
Correctable Read Memory Error SCI Enable: Generate
SCI when Bit 0 of DRAM_FERR or DRAM_NERR is set.
CRME_SCI _{0 = Disable}
N
1 = Enable
Bit Reset
Value
0b
0b
00b
0b
0b
0b
0b
Bit Access
RW
RW
RO
RW
RW
RW
RW
16.2.1.40 Offset 8Ah: DRAM_SMICMD - DRAM SMI Command Register
This register enables the memory controller to generate an SMI NSI special cycle for
various error flags. When an error flag is set in either the DRAM_FERR or DRAM_NERR
registers (see Section 16.2.1.36, “Offset 80h: DRAM_FERR - DRAM First Error Register”
and Section 16.2.1.37, “Offset 82h: DRAM_NERR - DRAM Next Error Register”),
hardware generates an SMI NSI special cycle when enabled in the DRAM_SMICMD
register.
Note that software should enable one and only one message type for a given error flag.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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