EP80579 Datasheet, PDF (451/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
16.2.1.11 Offset 2Eh: SID - Subsystem Identification Register
This value is used to identify a particular subsystem.
Table 16-65. Offset 2Eh: SID - Subsystem Identification Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:0:1
Offset Start: 2Eh
Offset End: 2Fh
Size: 16 bit
Default: 0000h
Power Well: Core
Bit Range Bit Acronym
Bit Description
15 : 00
SUBID
Subsystem ID: This field must be programmed during
BIOS initialization.
Sticky
Bit Reset
Value
Bit Access
0000h
RWO
16.2.1.12 Offset 40h: GLOBAL_FERR - Global First Error Register
This register is used to log various error conditions at the “unit” level. These bits are
“sticky” through reset, and are set regardless of whether or not any error messages
(SCI, SMI, SERR#, MCERR#) are enabled and generated at the unit level. Specific error
conditions within the various functional units are logged in the unit-specific error
registers that follow.
This register captures the FIRST global Fatal and the FIRST global Non-Fatal errors. For
these global error registers, a non-fatal error can be either an uncorrectable error
which is non-fatal, or a correctable error. Any future errors (NEXT errors) are captured
in the Global_NERR register. No further error bits in this register are set until the
existing error bit is cleared.
Note:
If multiple errors are reported in the same clock as the first error, all errors are latched.
Table 16-66. Offset 40h: GLOBAL_FERR - Global First Error Register (Sheet 1 of 2)
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:0:1
Offset Start: 40h
Offset End: 43h
Size: 32 bit
Default: 00000000h
Power Well: Core
Bit Range
31 : 28
27
26
25
Bit Acronym
Bit Description
Sticky
Reserved Reserved
DRAM Controller Channel Fatal Error: This bit is sticky
through reset. System software clears this bit by writing a
DRAM_FE ^{1 to the location.}
Y
0 = No fatal DRAM I/F error.
1 = The IMCH detected a fatal DRAM interface error.
Host (FSB) Fatal Error: This bit is sticky through reset.
System software clears this bit by writing a 1 to the
FSB_FE ^location.
Y
0 = No fatal FSB error.
1 = The IMCH detected a fatal FSB error.
NSI Fatal Error: This bit is sticky through reset. System
software clears this bit by writing a 1 to the location.
NSI_FE
0 = No fatal NSI error.
Y
1 = The IMCH detected a fatal NSI error.
Bit Reset
Value
0b
0b
0b
0b
Bit Access
RWC
RWC
RWC
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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