EP80579 Datasheet, PDF (1351/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
37.4.3.10 Diagnostics
To assist in test and debug of device-driver software, a set of software-usable features
have been provided. These features include controls for specific test-mode usage, as
well as some registers for verifying device internal state against what the device-driver
might be expecting.
The GbE provides software visibility (and controllability) into certain major internal data
structures, including all of the transmit & receive FIFO space. However, interlocks are
not provided for any operations, so diagnostic accesses should only be performed
under very controlled circumstances.
The device also provides software-controllable support for certain loopback modes, to
allow a device-driver to test transmit and receive flows to itself. Loopback modes may
also be used to diagnose communication problems and attempt to isolate the location
of a break in the communications path.
37.4.3.10.1 FIFO Pointer Accessibility
The internal pointers into the transmit and receive data FIFOs are visible through the
head and tail diagnostic data FIFO registers. Diagnostic software may read these FIFO
pointers to confirm an expected hardware state following a sequence of operations.
Diagnostic software may further write to these pointers as a partial-step to verify
expected FIFO contents following specific operation, or to subsequently write data
directly to the data FIFOs.
37.4.3.10.2 FIFO Data Accessibility
The internal transmit and receive data FIFO contents are accessible through the Packet
Buffer Memory (64KB) (PBM[n]) registers. The specific locations read/written are
determined by the values of the FIFO pointers, which may also be read/written. When
accessing the actual FIFO data structures, locations must be accessed as 32-bit words.
37.4.3.10.3 Loopback Operations
Loopback transmit/receive operation is a recommended debug tool. There are two
points where the transmit data can be looped back to the receive path: in the PHY and
in the MAC.
It is highly recommended that the PHY selected to interface with the GbE has
implemented loopback operations in order to assist with system and device debug.
Loopback operation may be used to test transmit & receive aspects of software drivers,
as well as verify electrical integrity of the connections between the GbE and the
system.
All loopback modes are only allowed when the MAC and PHY are configured for full
duplex operation.
37.5
Functional Description
37.5.1
Ethernet Addressing
Several registers store Ethernet addresses in the GbE. Two 32-bit registers make up
the address, the “high” and the “low”. For example, the Receive Address Register is
comprised of Receive Address High (RAH) and Receive Address Low (RAL). The least
significant bit of the least significant byte of the address stored in the register (i.e., bit
0 of RAL) is the multicast bit. The LS byte is the first byte to appear on the wire. This
notation applies to all Ethernet address registers including flow control.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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