EP80579 Datasheet, PDF (845/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 23-39. Offset E0h: BFCS – BIST FIS Control/Status Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:31:2
Offset Start: E0h
Offset End: E3h
Size: 32 bit
Default: 00000000h
Power Well: Core
Bit Range
08
Bit Acronym
Bit Description
Sticky
P0BFI
Port 0 BIST FIS Initiate (P0BFI): When a rising edge is
detected on this bit, the SATA controller will initiate a BIST
FIS to the device on port 0, using the parameters specified
in this register and BFTD1 and BFTD2. The BIST FIS will
only be initiated if a device is present and not in the
partial or slumber states. After a BIST FIS is successfully
completed, software must disable and re-enable PCS.P0E
prior to attempting additional BIST FISes or to return the
SATA controller to a normal operational mode. If the BIST
FIS fails, as indicated by BFF in this register, software can
clear then set this bit to initiate another BIST FIS.
BIST FIS Parameters (BFP): These bits form the
contents of the upper 6 bits of the BIST FIS Pattern
Definition in the BIST FIS transmitted by the SATA
controller. This field is not port specific – its contents will
be used for any BIST FIS initiated on the SATA controller.
The specific bit definitions are:
Bit Reset
Value
0h
Bit Access
RW
07 : 02
Bit
Symbol Description
7
T
Far End Transmit mode
BFP
6
A
Align Bypass mode
5
S
Bypass Scrambling
4
L
Far End Retimed Loopback
3
F
Far End Analog Loopback
2
P
Primitive bit for use with
Transmit mode
00h
RW
01 : 00
Reserved Reserved.
00h
RO
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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