EP80579 Datasheet, PDF (76/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Contents
34-19
34-20
34-21
34-22
34-23
34-24
34-25
34-26
34-27
34-28
34-29
34-30
34-31
34-32
34-33
34-34
34-35
34-36
34-37
35-1
35-2
35-3
35-4
35-5
35-6
35-7
35-8
35-9
35-10
35-11
35-12
35-13
35-14
35-15
35-16
35-17
35-18
35-19
35-20
35-21
35-22
35-23
35-24
35-25
35-26
35-27
35-28
35-29
35-30
35-31
35-32
35-33
Offset 1Dh: IOL: I/O Limit Register ................................................................. 1223
Offset 1Eh: SECSTA: Secondary Status Register ............................................... 1223
Offset 20h: MEMB: Memory Base Register ........................................................ 1224
Offset 22h: MEML: Memory Limit Register ........................................................ 1224
Offset 24h: PMASE: Prefetchable Memory Base Register .................................... 1225
Offset 26h: PMLIMIT: Prefetchable Memory Limit Register .................................. 1225
Offset 28h: PMBASU: Memory Limit Register .................................................... 1226
Offset 2Ch: PMLMTU: Prefetchable Memory Limit Upper Register ......................... 1226
Offset 30h: IOBU: I/O Base Upper Register ...................................................... 1227
Offset 32h: IOLU: I/O Limit Upper Register ...................................................... 1227
Offset 34h: CP: Capabilities Pointer Register ..................................................... 1227
Offset 3Ch: IRQL: Interrupt Line Register ......................................................... 1228
Offset 3Dh: IRQP: Interrupt Pin Register .......................................................... 1228
Offset 3Eh: BCTL: Bridge Control Register ........................................................ 1228
Offset DCh: PCID: Power Management Capability ID Register ............................. 1229
Offset DDh: PCP: Power Management Next Capability Pointer Register ................. 1230
Offset DEh: PMCAP: Power Management Capability Register ............................... 1230
Offset E0h: PMCS: Power Management Control and Status Register ..................... 1231
Offset E2h: PMCSE: Power Management Control and Status Extension Register ..... 1232
Type 0 PCI Configuration Header .................................................................... 1233
Messaging and Signalling Capability Record per PCI Device ................................ 1235
Bus M, Device 0, Function 0: Summary of Gigabit Ethernet MAC Interface PCI
Configuration Registers ................................................................................... 1237
Bus M, Device 1, Function 0: Summary of Gigabit Ethernet MAC Interface PCI
Configuration Registers ................................................................................... 1238
Bus M, Device2, Function 0: Summary of Gigabit Ethernet MAC Interface PCI Configuration
Registers ....................................................................................................... 1239
Offset 00h: VID: Vendor Identification Register ................................................. 1241
Offset 02h: DID: Device Identification Register ................................................. 1241
Offset 02h: DID: Device Identification Register ................................................. 1242
Offset 02h: DID: Device Identification Register ................................................. 1242
Offset 04h: PCICMD: Device Command Register ............................................... 1243
Offset 06h: PCISTS: PCI Device Status Register ................................................ 1244
Offset 08h: RID: Revision ID Register .............................................................. 1245
Offset 09h: CC: Class Code Register ................................................................ 1245
Offset 0Eh: HDR: Header Type Register ........................................................... 1246
Offset 10h: CSRBAR: Control and Status Registers Base Address Register ............ 1246
Offset 14h: IOBAR: CSR I/O Mapped BAR Register ............................................ 1247
Offset 2Ch: SVID: Subsystem Vendor ID Register ............................................. 1248
Offset 2Eh: SID: Subsystem ID Register .......................................................... 1248
Offset 34h: CP: Capabilities Pointer Register ..................................................... 1249
Offset 3Ch: IRQL: Interrupt Line Register ......................................................... 1249
Offset 3Dh: IRQP: Interrupt Pin Register .......................................................... 1250
Offset DCh: PCID: Power Management Capability ID Register ............................. 1251
Offset DDh: PCP: Power Management Next Capability Pointer Register ................. 1251
Offset DEh: PMCAP: Power Management Capability Register ............................... 1252
Offset E0h: PMCS: Power Management Control and Status Register ..................... 1253
Offset E4h: SCID: Signal Target Capability ID Register ...................................... 1254
Offset E5h: SCP: Signal Target Next Capability Pointer Register .......................... 1254
Offset E6h: SBC: Signal Target Byte Count Register .......................................... 1255
Offset E7h: STYP: Signal Target Capability Type Register ................................... 1255
Offset E8h: SMIA: Signal Target IA Mask Register ............................................. 1256
Offset ECh: SINT: Signal Target Raw Interrupt Register ...................................... 1257
Offset F0h: MCID: Message Signalled Interrupt Capability ID Register .................. 1258
Offset F1h: MCP: Message Signalled Interrupt Next Capability Pointer Register ..... 1258
Intel^® EP80579 Integrated Processor Product Line Datasheet
76
August 2009
Order Number: 320066-003US