EP80579 Datasheet, PDF (1472/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
37.6.3.12 IMS2 – Error Interrupt Mask Set/Read Register
This register contains which interrupts are enabled. An interrupt is enabled if its
corresponding mask bit is set to 1, and disabled if its corresponding mask bit is set to
0. An interrupt is generated whenever one of the bits in this register is set, and the
corresponding interrupt condition occurs, see the “ICR0 – Interrupt 0 Cause Read
Register” on page 1454 for interrupt conditions.
A particular interrupt may be enabled by writing a 1 to the corresponding mask bit in
this register. Any bits written with a 0, are unchanged. Thus, if software desires to
disable a particular interrupt condition that had been previously enabled, it must write
to the Interrupt Mask Clear Register rather than writing a 0 to a bit in this register.
Table 37-48. IMS2: Error Interrupt Mask Set/Read Register
Description:
View: PCI 1
BAR: CSRBAR
Bus:Device:Function: M:0:0
Offset Start: 08F0h
Offset End: 08F3h
View: PCI 2
BAR: CSRBAR
Bus:Device:Function: M:1:0
Offset Start: 08F0h
Offset End: 08F3h
View: PCI 3
BAR: CSRBAR
Bus:Device:Function: M:2:0
Offset Start: 08F0h
Offset End: 08F3h
Size: 32 bits
Default: 00000000h
GbE0: Aux
Power Well: Gbe1/2:
Core
Bit Range Bit Acronym
Bit Description
31 : 29
28
27
26
25 : 24
23
22
21
20
19 : 00
Rsvd
Reserved
ERR_INTBUS Enables Internal Bus Error
ERR_STAT Enables Statistic Register ECC Error
ERR_MCFSPF Enables Special Packet Filter Parity Error
Rsvd
Reserved
ERR_PKBUF Enables DMA Packet Buffer ECC Error
Rsvd
Reserved
ERR_TXDS Enables DMA Transmit Descriptor Buffer ECC Error
ERR_RXDS Enables DMA Receive Descriptor Buffer ECC Error
Rsvd
Reserved
Sticky
Bit Reset
Value
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
Bit Access
RV
RW
RW
RW
RV
RW
RV
RW
RW
RV
Intel^® EP80579 Integrated Processor Product Line Datasheet
1472
August 2009
Order Number: 320066-003US