EP80579 Datasheet, PDF (1359/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
• Explicit software flush (RDTR.FPD)
When the numbers of descriptors specified by RXDCTL.WTHRESH have been used, they
are written back, regardless of cacheline alignment It is therefore recommended that
WTHRESH be a multiple of cacheline size. When a receive timer (RADV or RDTR)
expires, all used descriptors are forced to be written back prior to initiating the
interrupt, for consistency. Software may explicitly flush accumulated descriptors by
writing the RDTR register with the high order bit (FPD) set.
37.5.5.5.2
Null Descriptor Padding
Hardware stores no data in descriptors with a null data address. Software can make
use of this property to cause the first condition under receive descriptor packing to
occur early. Hardware writes back null descriptors with the DD bit set in the status byte
and all other bits unchanged.
37.5.5.6 Receive Descriptor Queue Structure
Figure 37-10.Receive Descriptor Ring Structure
Circular Buffer
Base
Head
Receive
Queue
Tail
Base + Size
Figure 37-10 shows the structure of the receive descriptor ring. Hardware maintains a
circular queue of descriptors and writes back used descriptors just prior to advancing
the head pointer. Head and tail pointers wrap back to base when “size” descriptors have
been processed.
Software adds receive descriptors by advancing the tail pointer to refer to the address
of the entry just beyond the last valid descriptor. This is accomplished by writing the
descriptor tail register with the offset of the entry beyond the last valid descriptor. The
hardware adjusts its internal tail pointer accordingly. As packets arrive, they are stored
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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