EP80579 Datasheet, PDF (1089/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
27.8.2
Note:
RI# – Ring Indicate Signal
The Ring Indicator can cause a wake event (if enabled) from the S1, S3, S4 or S5
states. Table 27-36 shows when the wake event is generated or ignored in different
states. If in the G0/S0/Cx states, CMI generates an interrupt based on RI# active, and
the interrupt will be set up as a Break event.
There is no filtering on the RI# signal. Any debounce filtering must be done externally.
Table 27-36. Transitions Due to RI# Signal
Present State
S0
Event
RI# Active
S1, S3, S4, S5
RI# Active
RI_EN
X
0
1
Ignored
Ignored
Wake Event
Event
27.8.3
PME# – PCI Power Management Event
The PME# signal comes from a PCI device to request that the system be restarted. The
PME# signal can generate an SMI, SCI, or optionally a Wake event. The event occurs
when the PME# signal goes from high to low. No event is caused when it goes from low
to high.
27.8.4
SYS_RESET# Button
When the SYS_RESET# button is detected as active after the debounce logic (100 ms
debounce on the input, same as PWRBTN#), CMI will attempt to perform a “graceful”
reset, by waiting up to 25 ms, +/- 2ms for SM Bus to go idle. If SM Bus is idle when the
button is detected active, the reset will occur immediately, otherwise the counter will
start. If at any point during the count SM Bus goes idle, the counter will be reset and
the full system reset will occur. If, however, the counter expires and SM Bus is still
active, a full system reset will be forced upon the system even though SMBus activity is
still occurring.
Once the reset is asserted, it will remain asserted for approximately 1 ms, regardless of
whether the SYS_RESET# input remains asserted or not. It cannot occur again until
SYS_RESET# has been detected inactive after the debounce logic, and the system is
back to a full S0 state with PLTRST# inactive.
Note:
If bit 3 of the CF9h I/O register is set then SYS_RESET# will result in a full power cycle
reset.
27.8.5
Processor Thermal Trip
If THRMTRIP# goes active, the processor is indicating an overheat condition, and will
immediately transition to an S5 state. However, since the processor has overheated, it
will not respond to the STPCLK# pin with a stop grant special cycle. Therefore, CMI will
not wait for one. Immediately upon seeing THRMTRIP# low, CMI will initiate a transition
to the S5 state, drive signals SLP_S3#, SLP_S4#, SLP_S5# low, and set the CTS bit.
The transition will generally look like a power button override.
When a THRMTRIP# event occurs, CMI will power down immediately without following
the normal S0 -> S5 path.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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