EP80579 Datasheet, PDF (1723/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
46.2.2
46.2.2.1
Test Mode Registers
TEST0 - Test Control Register 0
Table 46-2. Test Control Register 0
Description:
View: STM
Base Address: NA
Size: 32 bit
Default:
000100001000000000000000
00000000
Bit Range
31
30
29
28
27
26
25 :24
23
22
21 :19
18
17
16
15
14 :13
12
11
10
09
08
07
06
05 :04
03 :01
00
Bit Acronym
Bit Description
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved.
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
XOR
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
XOR mode enable. Refer to Section 46.2.3 for more
information.
Reserved
Reserved
Reserved
Reserved
Reserved
Offset Start: NA
Offset End: NA
Power Well: Core
Sticky
Y
Bit Reset
Value
0b
0b
0b
1b
0b
00b
0b
1b
000b
0b
0b
0b
0b
00b
0b
0b
0b
0b
0b
0b
0b
00b
000b
0b
Bit Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
WO
RW
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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