EP80579 Datasheet, PDF (268/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
10.1.1 System Memory Spaces
Table 10-2. System Memory Space
From
DOSMEM
0_0000_0000
MEM1_15
0_0010_0000
MAINMEM
0_0100_0000
HIGHMEM
1_0000_0000
To
0_0009_FFFF
0_00EF_FFFF
TOLM
7_FFFF_FFFF
Table 10-2’s address ranges are always mapped to system memory, regardless of the
system configuration. The Top of Low Memory (TOLM) register (see Section 16.1.1.30,
“Offset C4h: TOLM - Top of Low Memory Register”) provides a mechanism to carve
memory out of the MAINMEM segment for use by System Management Mode (SMM)
hardware and software, PCI add-in devices, and other functions. The address of the
highest 128 MByte quantity of populated DRAM memory in the system is placed into
the DRB3 register, which will match the value in the Top of Memory (TOM) register (see
Section 16.1.1.34, “Offset CCh: TOM - Top Of Memory Register”.
10.1.2
VGA and MDA Memory Spaces
Table 10-3 lists the VGA and MDA Memory spaces. Figure 10-2 illustrates the DOS
legacy Region.
Table 10-3. IMCH VGA and MDA Memory Spaces
From
To
VGAA
0_000A_0000
0_000A_FFFF
MDA
0_000B_0000
0_000B_7FFF
VGAB
0_000B_8000
0_000B_FFFF
Note:
These legacy address ranges are used on behalf of video cards to map a frame buffer or
a character-based video buffer into a dedicated location. By default, accesses to these
ranges are forwarded to the NSI. However, if the VGAEN bit is set in one of the BCTRL
configuration registers (see Section 16.4.1.26, “Offset 3Eh: BCTRL - Bridge Control
Register”), then transactions within the VGA and MDA spaces are sent to one of the PCI
Express interfaces in IMCH.
The VGAEN bit may be set in one and only one of the BCTRL registers. Software must
not set more than one VGAEN bit.
Intel^® EP80579 Integrated Processor Product Line Datasheet
268
August 2009
Order Number: 320066-003US