EP80579 Datasheet, PDF (486/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 16-92. Offset 84h: DRAM_EMASK - DRAM Error Mask Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:0:1
Offset Start: 84h
Offset End: 84h
Size: 8 bit
Default: 00h
Power Well: Core
Bit Range
07
06
05 :04
03
02
01
00
Bit Acronym
Bit Description
Sticky
Memory Test Complete Mask: This bit is sticky through
reset.
MTC_MASK ^{0 = Allow Memory Test Complete logging and signaling.}
Y
1 = Mask Memory Test Complete logging and signaling.
Mask Error bits 7.
Uncorrectable Error Detected on Write to DRAM
Mask: This bit is sticky through reset.
UERR_MASK 0 = Allow Poisoned Write to DRAM detection and signaling. Y
1 = Mask Poisoned Write to DRAM detection and signaling.
Mask Error bit 6.
Reserved Reserved
Error Threshold Detect Mask: This bit is sticky through
reset.
ETD_MASK ^{0 = Allow Error Threshold detection and signaling.}
Y
1 = Mask Error Threshold detection and signaling.
Mask Error bit 3.
Scrubber Data Error Mask: This bit is sticky through
reset.
SDE_MASK ^{0 = Allow Scrubber Data Error detection and signaling.}
Y
1 = Mask Scrubber Data Error detection and signaling.
Mask Error bit 2.
Uncorrectable Read Memory Error Mask: This bit is
sticky through reset.
0 = Allow Uncorrectable Memory Read Error detection and
URME_MASk
signaling.
Y
1 = Mask Uncorrectable Memory Read Error detection and
signaling.
Mask Error bit 1.
Correctable Read Memory Error Mask: This bit is sticky
through reset.
0 = Allow Correctable Memory Read Error detection and
CRME_MASK
signaling.
Y
1 = Mask Correctable Memory Read Error detection and
signaling.
Mask Error bit 0.
Bit Reset
Value
0b
0b
00b
0b
0b
0b
0b
Bit Access
RW
RW
RW
RW
RW
RW
RW
16.2.1.39 Offset 88h: DRAM_SCICMD - DRAM SCI Command Register
This register enables the memory controller to generate an SCI NSI special cycle for
various error flags. When an error flag is set in either the DRAM_FERR or DRAM_NERR
registers (see Section 16.2.1.36, “Offset 80h: DRAM_FERR - DRAM First Error Register”
and Section 16.2.1.37, “Offset 82h: DRAM_NERR - DRAM Next Error Register”),
hardware generates an SCI NSI special cycle when enabled in the DRAM_SCICMD
register.
Note that software should enable one and only one message type for a given error flag.
Intel^® EP80579 Integrated Processor Product Line Datasheet
486
August 2009
Order Number: 320066-003US