EP80579 Datasheet, PDF (956/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 25-22. Run/Stop, Debug Bit Interaction SWDBG (Bit 5), Run/Stop (Bit 0) Operation
SWDBG
(Bit 5)
Run/
Stop
(Bit 0)
Description
If executing a command, the Host Controller completes the command and then stops.
0
0
The 1.0 ms frame counter is reset and command list execution resumes from start of
frame using the frame list pointer selected by the current value in the FRNUM register.
(While Run/Stop=0, the FRNUM register can be reprogrammed).
Execution of the command list resumes from Start Of Frame using the frame list pointer
0
1
selected by the current value in the FRNUM register. The Host Controller remains running
until the Run/Stop bit is cleared (by Software or Hardware).
If executing a command, the Host Controller completes the command and then stops
1
0
and the 1.0 ms frame counter is frozen at its current value. All status are preserved. The
Host Controller begins execution of the command list from where it left off when the
Run/Stop bit is set.
Execution of the command list resumes from where the previous execution stopped. The
1
1
Run/Stop bit is set to 0 by the Host Controller when a TD is being fetched. This causes
the Host Controller to stop again after the execution of the TD (single step). When the
Host Controller has completed execution, the HC Halted bit in the Status Register is set.
When the USB Host Controller is in Software Debug Mode (USBCMD Register bit 5=1),
the single stepping software debug operation is as follows:
To Enter Software Debug Mode:
1. HCD puts Host Controller in Stop state by setting the Run/Stop bit to 0.
2. HCD puts Host Controller in Debug Mode by setting the SWDBG bit to 1.
3. HCD sets up the correct command list and Start Of Frame value for starting point in
the Frame List Single Step Loop:
4. HCD sets Run/Stop bit to 1.
5. Host Controller executes next active TD, sets Run/Stop bit to 0, and stops.
6. HCD reads the USBCMD register to check if the single step execution is completed
(HCHalted=1).
7. HCD checks results of TD execution. Go to step 4 to execute next TD or step 8 to
end Software Debug mode.
8. HCD ends Software Debug mode by setting SWDBG bit to 0.
9. HCD sets up normal command list and Frame List table.
10. HCD sets Run/Stop bit to 1 to resume normal schedule execution.
In Software Debug mode, when the Run/Stop bit is set, the Host Controller starts.
When a valid TD is found, the Run/Stop bit is reset. When the TD is finished, the
HCHalted bit in the USBSTS register (bit 5) is set.
The software Debug mode skips over inactive TDs and only halts after an active TD has
been executed. When the last active TD in a frame has been executed, the Host
Controller waits until the next SOF is sent and then fetches the first TD of the next
frame before halting.
This HCHalted bit can also be used outside of Software Debug mode to indicate when
the Host Controller has detected the Run/Stop bit and has completed the current
transaction. Outside of the Software Debug mode, setting the Run/Stop bit to 0 always
resets the SOF counter so that when the Run/Stop bit is set the Host Controller starts
over again from the frame list location pointed to by the Frame List Index (see FRNUM
Register description) rather than continuing where it stopped.
Intel^® EP80579 Integrated Processor Product Line Datasheet
956
August 2009
Order Number: 320066-003US