EP80579 Datasheet, PDF (1544/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 37-144.FFVT[0-127]: Flexible Filter Value Table Registers
Description:
View: PCI 1
BAR: CSRBAR
Bus:Device:Function: M:0:0
Offset Start: 9800h at 8h
Offset End: 9803h at 8h
View: PCI 2
BAR: CSRBAR
Bus:Device:Function: M:1:0
Offset Start: 9800h at 8h
Offset End: 9803h at 8h
View: PCI 3
BAR: CSRBAR
Bus:Device:Function: M:2:0
Offset Start: 9800h at 8h
Offset End: 9803h at 8h
Size: 32 bits
Default: XXXXXXXXh
Power
Well:
GbE0: Aux
Gbe1/2: Core
Bit Range Bit Acronym
Bit Description
31 : 24
23 : 16
15 : 08
07 : 00
VAL3
VAL2
VAL1
VAL0
Byte x Compare Value 3
Byte x Compare Value 2
Byte x Compare Value 1
Byte x Compare Value 0
Sticky
Bit Reset
Value
X
X
X
X
Bit Access
RW
RW
RW
RW
Note:
Before writing to the Flexible Filter Length Table the driver must first disable the flexible
filters by writing 0's to the Flexible Filter Enable bits of the Wake Up Filter Control
Register (WUFC.FLXn)
37.6.8 Error Register Descriptions
37.6.8.1
INTBUS_ERR_STAT – Internal Bus Error Status Register
This register captures status information about errors that occur on the internal bus.
Table 37-145.INTBUS_ERR_STAT - Internal Bus Error Status Register (Sheet 1 of 2)
Description:
View: PCI 1
BAR: CSRBAR
Bus:Device:Function: M:0:0
Offset Start: 0510h
Offset End: 0513h
View: PCI 2
BAR: CSRBAR
Bus:Device:Function: M:1:0
Offset Start: 0510h
Offset End: 0513h
View: PCI 3
BAR: CSRBAR
Bus:Device:Function: M:2:0
Offset Start: 0510h
Offset End: 0513h
Size: 32 bits
Default: 00000000h
Power
Well:
GbE0: Aux
Gbe1/2: Core
Bit Range Bit Acronym
Bit Description
Sticky
31 : 13
12
Rsvd
Reserved
INTBUS_ERR_H
_DIS
0 - Internal Bus errors
receive operation.
1 - Internal Bus errors
will
will
halt further GbE transmit/
not halt further GbE operation.
Bit Reset
Value
0h
0
Bit Access
RV
RW
Intel^® EP80579 Integrated Processor Product Line Datasheet
1544
August 2009
Order Number: 320066-003US