EP80579 Datasheet, PDF (179/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 6-9.
Sleeping States
Sleeping
State
S0
S1
S2
S3
S4
S5 Soft Off
Description
Fully Active
The S1 sleeping state is a low wake latency sleeping state. In this state, no system context is
lost (CPU or chip set) and hardware maintains all system context.
The S2 sleeping state is a low wake latency sleeping state. This state is similar to the S1
sleeping state except that the CPU and system cache context is lost (the OS is responsible for
maintaining the caches and CPU context). Control starts from the processor's reset vector
after the wake event.
The S3 sleeping state is a low wake latency sleeping state where all system context is lost
except system memory. CPU, cache, and chip set context are lost in this state. Hardware
maintains memory context and restores some CPU and L2 configuration context. Control starts
from the processor's reset vector after the wake event.
The S4 sleeping state is the lowest power, longest wake latency sleeping state supported by
ACPI. In order to reduce power to a minimum, it is assumed that the hardware platform has
powered off all devices. Platform context is maintained.
The S5 state is similar to the S4 state except that the OS does not save any context. The
system is in the “soft” off state and requires a complete boot when it wakes. Software uses a
different state value to distinguish between the S5 state and the S4 state to allow for initial
boot operations within the BIOS to distinguish whether or not the boot is going to wake from a
saved memory image.
Table 6-10. CPU States
Processor
Power State
Description
C0 - Full On
Processor core is active. All clocks are running. Processor can maintain cache coherency via
snoops. Processor responds to interrupt.
C1 - Auto Halt
Processor Core is not active after executing an Auto-Halt instruction. Processor Core clock
is internally gated. Processor can maintain cache coherency via snoops. Processor
responds to interrupts. Aside from putting the processor in a non-executing power state,
this state has no other software-visible effects.
C2 - Stop Grant
Processor Core is not active after its STPCLK# input is asserted. Processor Core clock is
internally gated. Processor can maintain cache coherency via snoops. Processor responds
to interrupts. Aside from putting the processor in a non-executing power state, this state
has no other software-visible effects.
C3 - Deep Sleep
Processor Core is not active after its SLP# input is asserted. Processor Core clock is gated
and PLLs are disabled. Processor does not respond to snoops or interrupts. While in the C3
state, the processor's caches maintain state but ignore any snoops. The operating software
is responsible for ensuring that the caches maintain coherency. The EP80579 does not
support C3 while functioning in S0 state, however, while in S1 state, The EP80579 will put
the processor in Deep Sleep state through the assertion on the SLP# signal.
6.3.2
Power Management Support
As a system on a chip with embedded I/O devices and many SKUs, the EP80579 power
management needs to perform multiple functions (typically under ACPI and/or BIOS
system software control):
• Minimize power consumption of software-disabled interfaces/units.
• Transition between defined ACPI states as defined in Table 6-11.
• Support system wake-up from GPIO, PCI Express* devices and GbE MAC ports
(Wake-on-LAN).
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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