EP80579 Datasheet, PDF (203/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
7.3.5
PCI Express* Port A1 Registers: Bus 0, Device 3, Function 0
The PCI Express* Port A1 includes the registers listed in Table 7-16. These registers
materialize in PCI configuration space. See Section 16.4, “PCI Express* Port A
Standard and Enhanced Registers: Bus 0, Devices 2 and 3, Function 0” for detailed
discussion of these registers.
Table 7-16. Bus 0, Device 3, Function 0: Summary of PCI Express Port A1 Standard and
Enhanced PCI Configuration Registers (Sheet 1 of 3)
Offset Start Offset End
Register ID - Description
Default
Value
00h
02h
04h
06h
08h
0Ah
0Bh
0Ch
0Eh
18h
19h
1Ah
1Ch
1Dh
1Eh
20h
22h
24h
26h
28h
2Ch
34h
3Ch
3Dh
3Eh
44h
45h
46h
47h
48h
50h
01h
03h
05h
07h
08h
0Ah
0Bh
0Ch
0Eh
18h
19h
1Ah
1Ch
1Dh
1Fh
21h
23h
25h
27h
28h
2Ch
34h
3Ch
3Dh
3Eh
44h
45h
46h
47h
48h
50h
“Offset 00h: VID - Vendor Identification Register” on page 527
8086h
“Offset 02h: DID - Device Identification Register” on page 528
5025h
“Offset 04h: PCICMD - PCI Command Register” on page 528
0000h
“Offset 06h: PCISTS - PCI Status Register” on page 530
0010h
“Offset 08h: RID - Revision Identification Register” on page 531
Variable
“Offset 0Ah: SUBC - Sub-Class Code Register” on page 532
04h
“Offset 0Bh: BCC - Base Class Code Register” on page 532
06h
“Offset 0Ch: CLS - Cache Line Size Register” on page 533
00h
“Offset 0Eh: HDR - Header Type Register” on page 533
01h
“Offset 18h: PBUSN - Primary Bus Number Register” on page 534
00h
“Offset 19h: SBUSN - Secondary Bus Number Register” on page 534
00h
“Offset 1Ah: SUBUSN: Subordinate Bus Number Register” on page 535
00h
“Offset 1Ch: IOBASE - I/O Base Address Register” on page 535
F0h
“Offset 1Dh: IOLIMIT - I/O Limit Address Register” on page 536
00h
“Offset 1Eh: SECSTS - Secondary Status Register” on page 536
0000h
“Offset 20h: MBASE - Memory Base Address Register” on page 538
FFF0h
“Offset 22h: MLIMIT - Memory Limit Address Register” on page 539
0000h
“Offset 24h: PMBASE - Prefetchable Memory Base Address Register” on page 540 FFF1h
“Offset 26h: PMLIMIT - Prefetchable Memory Limit Address Register” on page 540 0001h
“Offset 28h: PMBASU - Prefetchable Memory Base Upper Address Register” on
page 541
0Fh
“Offset 2Ch: PMLMTU - Prefetchable Memory Limit Upper Address Register” on
page 541
00h
“Offset 34h: CAPPTR - Capabilities Pointer Register” on page 542
50h
“Offset 3Ch: INTRLINE - Interrupt Line Register” on page 542
00h
“Offset 3Dh: INTRPIN - Interrupt Pin Register” on page 543
01h
“Offset 3Eh: BCTRL - Bridge Control Register” on page 543
00h
“Offset 44h: VSCMD0 - Vendor Specific Command Byte 0 Register” on page 545 00h
“Offset 45h: VSCMD1 - Vendor Specific Command Byte 1 Register” on page 546 00h
“Offset 46h: VSSTS0 - Vendor Specific Status Byte 0 Register” on page 547
00h
“Offset 47h: VSSTS1 - Vendor Specific Status Byte 1 Register” on page 547
00h
“Offset 48h: VSCMD2 - Vendor Specific Command Byte 2 Register” on page 548 00h
“Offset 50h: PMCAPID - Power Management Capabilities Structure Register” on
page 548
01h
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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