EP80579 Datasheet, PDF (705/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 17-25. Offset 3400h: RC - RTC Configuration Register
Description:
View: PCI
BAR: RCBA
Bus:Device:Function: 0:31:0
Offset Start: 3400h
Offset End: 3403h
Size: 32 bit
Default: 0h
Power Well: Core
Bit Range
03
02
01 : 00
Bit Acronym
Bit Description
Sticky
LL
UE
Reserved
Lower 128 Byte Lock:
0 = Bytes 38h-3Fh in the lower 128-byte bank of RTC
RAM are not locked and can be accessed. Writes are
not dropped and reads return any guaranteed data.
1 = Bytes 38h-3Fh in the lower 128-byte bank of RTC
RAM are locked and cannot be accessed. Writes are
dropped and reads do not return any guaranteed
data. Bit reset on system reset.
Upper 128 Byte Enable:
0 = The upper 128-byte bank of RTC RAM can not be
accessed.
1 = The upper 128-byte bank of RTC RAM can be
accessed.
Reserved
Bit Reset
Value
0h
0h
0h
Bit Access
RWO
RW
17.1.6.2
Offset 3404h: HPTC - High Performance Precision Timer Configuration
Register
This register specifies the base address in memory space at which the High
Performance Precision Timer registers from Section 32.2.1, “Register Descriptions”
materialize.
Table 17-26. Offset 3404h: HPTC - High Performance Precision Timer Configuration
Register
Description:
View: PCI
BAR: RCBA
Bus:Device:Function: 0:31:0
Offset Start: 3404h
Offset End: 3407h
Size: 32 bit
Default: 0h
Power Well: Core
Bit Range
31 : 08
Bit Acronym
Reserved Reserved
Bit Description
Sticky
Bit Reset
Value
0h
Bit Access
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
705