EP80579 Datasheet, PDF (995/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 26-29. Offset 68h: ULSEC - USB 2.0 Legacy Support Extended Capability Register
(Sheet 2 of 2)
Description: Reset: suspend well, and not D3-to-D0 warm reset nor core well.
View: PCI
BAR: Configuration
Bus:Device:Function: 0:29:7
Offset Start: 68h
Offset End: 6Bh
Size: 32 bit
Default: 00000001h
Power Well: Suspend
Bit Range
16
15 :08
07 :00
Bit Acronym
Bit Description
Sticky
HC_BIOS
NEHCI
CAPID
Host Controller BIOS Owned Semaphore: The BIOS
sets this bit to establish ownership of the EHCI controller.
System BIOS will clear this bit in response to a request for
ownership of the EHCI controller by system software.
Next EHCI Capability Pointer: A value of 00h indicates
that there are no EHCI Extended Capability structures in
this device.
Capability ID: A value of 01h indicates that this EHCI
Extended Capability is the Legacy Support Capability.
Bit Reset
Value
0h
00h
01h
Bit Access
RW
RO
RO
26.2.1.28 Offset 6Ch: ULSCS - USB 2.0 Legacy Support Control/Status Register
Writing a ‘1’ to that bit location clears bits that are marked as Read/Write-Clear (RWC).
Table 26-30. Offset 6Ch: ULSCS - USB 2.0 Legacy Support Control/Status Register (Sheet 1
of 3)
Description: Lockable: Suspend well, and not D3-to-D0 warm reset nor core well.
View: PCI
BAR: Configuration
Bus:Device:Function: 0:29:7
Offset Start: 6Ch
Offset End: 6Fh
Size: 32bit
Default: 00000000h
Power Well: Suspend
Bit Range
31
30
29
28 :22
21
Bit Acronym
Bit Description
Sticky
SMI_BAR
SMI_PCMD
SMI_OSC
Reserved
SMI_AA
SMI on BAR:
0 = Base Address Register (BAR) not written.
1 = This bit is set to 1 when the Base Address Register
(BAR) is written.
SMI on PCI Command: This bit is set to ‘1’ whenever the
PCI Command Register is written.
0 = PCI Command (PCICMD) Register Not written.
1 = This bit is set to 1 when the PCI Command (PCICMD)
Register is written.
SMI on OS Ownership Change:
0 = No HC OS Owned Semaphore bit change.
1 = This bit is set to 1 when the HC OS Owned
Semaphore bit in the LEG_EXT_CAP register
(D29:F7:68h, bit 24) transitions from 1 to 0 or 0 to 1.
Reserved. Hardwired to 0.
SMI on Async Advance: Shadow bit of the Interrupt on
Async Advance bit in the USB 2.0STS register. To clear this
bit, system software must write a one to the Interrupt on
Async Advance bit in the USB 2.0STS register.
Bit Reset
Value
0h
0h
0h
00h
0h
Bit Access
RWC
RWC
RWC
RO
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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