EP80579 Datasheet, PDF (895/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
24.0
SMBus Controller Functional Description: Bus 0,
Device 31, Function 3
24.1
Overview
CMI’s IICH contains an SMBus Host interface that allows the processor to communicate
with SMBus slaves.
Table 24-1 lists the SMBus signals and the actions taken during various power events
Table 24-1. SMBus signals
Signal Name
Power
Plane
During
Reset
After
Reset
S3
S5
Alt Driver
SMBDATA
SMBCLK
Resume
Resume
See note
High-Z
High-Z
High-Z
High-Z
Peripherals
Peripherals
SMBALERT#
Resume
Can be driven high or low.
Peripherals
Note: SMBDATA and SMBCLK might go active if other devices are using the bus.
Unless specified, all of SMBus logic and registers in this chapter are reset by either CF9
reset or RSMRST#.
24.1.1
Host Controller
The CMI provides a System Management Bus (SMBus) Specification, Version 2.0-
compliant host controller. The host controller provides a mechanism for the processor
to initiate communications with SMB peripherals (slaves). The CMI is also capable of
operating in a mode in which it can communicate with I²C compatible devices.
The CMI can perform SMBus messages with either PEC enabled or disabled. The actual
PEC calculation and checking is performed in software. The SMBus Host Controller logic
can automatically append the CRC byte if configured to do so.
The CMI SMBus logic exists in Device 31, Function 3 configuration space, and consists
of a transmit data path and host controller. The transmit data path provides the data
flow logic needed to implement the seven different SMB command protocols and is
controlled by the host controller. The logic is clocked by the RTC clock.
The SMBus Address Resolution Protocol (ARP) is supported through software by using
the existing host controller commands, except for the new Host Notify command (which
is actually a received message).
The programming model of the host controller is combined into two portions: A PCI
configuration portion and a system I/O mapped portion. All static configuration, such as
the I/O base address, is done via the PCI configuration space. Real-time programming
of the host interface is done in system I/O space.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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