EP80579 Datasheet, PDF (1012/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 26-42. Offset 28h: USB2INTR - USB 2.0 Interrupt Enable Register
Description:
View: PCI
BAR: MBAR
Bus:Device:Function: 0:29:7
Offset Start: 28h
Offset End: 2Bh
Size: 32 bit
Default: 00000000h
Power Well: Core
Bit Range Bit Acronym
Bit Description
Sticky
31 :06
Reserved Reserved.
Interrupt on Async Advance Enable:
0 = Disable.
1 = When this bit is a one, and the Interrupt on Async
05
INT_AAEN
Advance bit in the USBSTS register is a one, the host
controller will issue an interrupt at the next interrupt
threshold. The interrupt is acknowledged by software
clearing the Interrupt on Async Advance bit.
Host System Error Enable:
0 = Disable.
1 = When this bit is a one, and the Host System Error
04
HSE_EN
Status bit in the USBSTS register is a one, the host
controller will issue an interrupt. The interrupt is
acknowledged by software clearing the Host System
Error bit.
Frame List Rollover Enable:
0 = Disable.
03
FLR_EN
1 = When this bit is a one, and the Frame List Rollover bit
in the USBSTS register is a one, the host controller
will issue an interrupt. The interrupt is acknowledged
by software clearing the Frame List Rollover bit.
Port Change Interrupt Enable:
0 = Disable.
02
PCI_EN
1 = When this bit is a one, and the Port Change Detect bit
in the USBSTS register is a one, the host controller
will issue an interrupt. The interrupt is acknowledged
by software clearing the Port Change Detect bit.
USB Error Interrupt Enable:
0 = Disable.
1 = When this bit is a one, and the USBERRINT bit in the
01
USBEI_EN
USBSTS register is a one, the host controller will
issue an interrupt at the next interrupt threshold. The
interrupt is acknowledged by software by clearing the
USBERRINT bit.
USB Interrupt Enable:
0 = Disable.
1 = When this bit is a one, and the USBINT bit in the
00
USBI_EN
USBSTS register is a one, the host controller will
issue an interrupt at the next interrupt threshold. The
interrupt is acknowledged by software by clearing the
USBINT bit.
Note: For all enable register bits, 1= Enabled, 0= Disabled
Bit Reset
Value
0h
0h
0h
0h
0h
0h
0h
Bit Access
RW
RW
RW
RW
RW
RW
Intel^® EP80579 Integrated Processor Product Line Datasheet
1012
August 2009
Order Number: 320066-003US