EP80579 Datasheet, PDF (1256/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
35.6.1.25 Offset E8h: SMIA – Signal Target IA Mask Register
Table 35-30. Offset E8h: SMIA: Signal Target IA Mask Register
Description:
View: PCI 1
BAR: Configuration
Bus:Device:Function: M:0:0
Offset Start: E8h
Offset End: E8h
View: PCI 2
BAR: Configuration
Bus:Device:Function: M:1:0
Offset Start: E8h
Offset End: E8h
View: PCI 3
BAR: Configuration
Bus:Device:Function: M:2:0
Offset Start: E8h
Offset End: E8h
Size: 8 bit
Default: 0h
Power Well: Core
Bit Range
07 : 03
02
01
00
Bit Acronym
Bit Description
Sticky
Reserved
SMIA2
SMIA1
SMIA0
IA mask bit: If set to 1h, an interrupt is sent to the IA as
either an INTx or MSI based on the PCI signaling
configuration when detect gbex_interrupt0 which carries
all interrupt sources (functional plus AIOC internal bus
errors and internal memory errors) and the functional
interrupts are throttled by a timer
IA mask bit: If set to 1h, an interrupt is sent to the IA as
either an INTx or MSI based on the PCI signaling
configuration when detect gbex_interrupt1 which carries
all interrupt sources (functional plus AIOC internal bus
errors and internal memory errors) but the functional
interrupts are not throttled
IA mask bit: If set to 1h, an interrupt is sent to the IA as
either an INTx or MSI based on the PCI signaling
configuration when detect gbex_error_interrupt which
carries only AIOC internal bus errors and internal memory
parity or uncorrectable ECC errors
Bit Reset
Value
0h
0h
0h
0h
Bit Access
RW
RW
RW
RW
35.6.1.26 Offset E9h: Reserved Register
Writing to this register will result in undefined behavior.
35.6.1.27 Offset EAh: Reserved Register
Writing to this register will result in undefined behavior.
Intel^® EP80579 Integrated Processor Product Line Datasheet
1256
August 2009
Order Number: 320066-003US