EP80579 Datasheet, PDF (1221/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
34.2.2.11 Offset 14h: CSRBAR1 – Control and Status Registers Base Address
Register
Table 34-13. Offset 14h: CSRBAR1: Control and Status Registers Base Address Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:4:0
Offset Start: 14h
Offset End: 17h
Size: 32 bit
Default: 00h
Power Well: Core
Bit Range Bit Acronym
Bit Description
31 : 04
03
02 : 01
00
ZERO
PREF
TYP
MEM
These bits of the address are hardwired to zero for 128
Kbyte.
Prefetchable
BAR Type (64-bit)
Memory Space Indicator
Sticky
Bit Reset
Value
Bit Access
0h
RO
0h
RO
0b
RO
0h
RO
34.2.2.12 Offset 18h: PBNUM – Primary Bus Number Register
Table 34-14. Offset 18h: PBNUM: Primary Bus Number Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:4:0
Offset Start: 18h
Offset End: 18h
Size: 8 bit
Default: 00h
Power Well: Core
Bit Range Bit Acronym
Bit Description
07 : 00
PBNUM Primary Bus Number
Sticky
Bit Reset
Value
0h
Bit Access
RW
34.2.2.13 Offset 19h: SECBNM – Secondary Bus Number Register
Table 34-15. Offset 19h: SECBNM: Secondary Bus Number Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:4:0
Offset Start: 19h
Offset End: 19h
Size: 8 bit
Default: 00h
Power Well: Core
Bit Range Bit Acronym
Bit Description
07 : 00
SECBNM Secondary Bus Number
Sticky
Bit Reset
Value
0h
Bit Access
RW
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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