EP80579 Datasheet, PDF (540/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 16-158.Offset 24h: PMBASE - Prefetchable Memory Base Address Register
Description:
View: PCI 1
BAR: Configuration
Bus:Device:Function: 0:2:0
Offset Start: 24h
Offset End: 25h
View: PCI 2
BAR: Configuration
Bus:Device:Function: 0:3:0
Offset Start: 24h
Offset End: 25h
Size: 16 bit
Default: FFF1h
Power Well: Core
Bit Range
15 : 04
03 : 01
00
Bit Acronym
Bit Description
Sticky
PMBASE
MAMB
MBUAE
Prefetchable Memory Address Base: Corresponds to
A[31:20] of the lower limit of the address range passed by
bridge device across PCI Express*.
Memory Addressing Mode. These bits are read-only with
a value of zero, all other values are reserved.
Memory Base Upper Address Enabled:
0 = Disabled
1 = Enabled - Indicates that the base address is further
defined by the upper address bits of the memory base
upper address register.
Bit Reset
Value
FFFh
0h
1h
Bit Access
RW
RO
RO
16.4.1.20 Offset 26h: PMLIMIT - Prefetchable Memory Limit Address Register
This register controls the processor to PCI Express* prefetchable memory accesses.
The upper 12 bits of the register are read/write and correspond to the upper 12
address bits A[31:20] of the 32-bit address. For the purpose of address decode, bits
A[19:00] are assumed to be FFFFFh. Thus, the top of the defined memory address
range are at the top of a 1 Mbyte aligned memory block.
Table 16-159.Offset 26h: PMLIMIT - Prefetchable Memory Limit Address Register
Description:
View: PCI 1
BAR: Configuration
Bus:Device:Function: 0:2:0
Offset Start: 26h
Offset End: 27h
View: PCI 2
BAR: Configuration
Bus:Device:Function: 0:3:0
Offset Start: 26h
Offset End: 27h
Size: 16 bit
Default: 0001h
Power Well: Core
Bit Range
15 : 04
03 : 01
00
Bit Acronym
Bit Description
Sticky
PMLIMIT
MAML
MLUAE
Prefetchable Memory Address Limit: Corresponds to
A[31:20] of the upper limit of the address range passed by
bridge Device 2 across PCI Express*.
Memory Addressing Mode. These bits are read-only with
a value of zero, all other values are reserved.
Memory Limit Upper Address Enabled:
0 = Disabled
1 = Enabled - Indicates that the limit address is further
expanded/defined by the upper address bits of the
memory limit upper address register.
Bit Reset
Value
000h
0h
1h
Bit Access
RW
RO
RO
Intel^® EP80579 Integrated Processor Product Line Datasheet
540
August 2009
Order Number: 320066-003US