EP80579 Datasheet, PDF (861/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 23-60. Offset 110h: PxIS[0-1] – Port [0-1] Interrupt Status Register (Sheet 2 of 2)
Description:
View: PCI
BAR: ABAR
Bus:Device:Function: 0:31:2
Offset Start: 110h, 190h
Offset End: 113h, 193h
Size: 32 bit
Default: 00000000h
Power Well: Core
Bit Range
04
03
02
01
00
Bit Acronym
Bit Description
Sticky
UFS
SDBS
DSS
PSS
DHRS
Unknown FIS Interrupt (UFS): When set to ‘1’
indicates that an unknown FIS was received and has been
copied into system memory. This bit is cleared to ‘0’ by
software clearing the PxSERR.DIAG.F bit to ‘0’. Note that
this bit does not directly reflect the PxSERR.DIAG.F bit.
PxSERR.DIAG.F is set immediately when an unknown FIS
is detected, whereas this bit is set when the FIS is posted
to memory. Software should wait to act on an unknown
FIS until this bit is set to ‘1’ or the two bits may become
out of sync.
Set Device Bits Interrupt (SDBS): A Set Device Bits
FIS has been received with the ‘I’ bit set and has been
copied into system memory.
DMA Setup FIS Interrupt (DSS): A DMA Setup FIS has
been received with the ‘I’ bit set and has been copied into
system memory.
PIO Setup FIS Interrupt (PSS): A PIO Setup FIS has
been received with the ‘I’ bit set, it has been copied into
system memory, and the data related to that FIS has been
transferred. This bit shall be set even if the data transfer
resulted in an error.
Device to Host Register FIS Interrupt (DHRS): A D2H
register FIS has been received with the ‘I’ bit set, and has
been copied into system memory.
Bit Reset
Value
0h
0h
0h
0h
0h
Bit Access
RO
RWC
RWC
RWC
RWC
23.3.3.6
Offset 114h: PxIE[0-1] – Port [0-1] Interrupt Enable Register
This register enables and disables the reporting of the corresponding interrupt to
system software. When a bit is set (‘1’) and the corresponding interrupt condition is
active, then an interrupt is generated. Interrupt sources that are disabled (‘0’) are still
reflected in the status registers. This register is symmetrical with the Port 0 Status
register.
Table 23-61. Offset 114h: PxIE[0-1] – Port [0-1] Interrupt Enable Register (Sheet 1 of 2)
Description:
View: PCI
BAR: ABAR
Bus:Device:Function: 0:31:2
Offset Start: 114h, 194h
Offset End: 117h, 197h
Size: 32 bit
Default: 00000000h
Power Well: Core
Bit Range
31
30
29
Bit Acronym
Bit Description
Sticky
CPDE
TFEE
HBFE
Cold Presence Detect Enable (CPDE): The SATA
controller does not support cold presence detect.
Task File Error Enable (TFEE): When set, GHC.IE is set,
and P0S.TFES is set, the HBA shall generate an interrupt.
Host Bus Fatal Error Enable (HBFE): When set, GHC.IE
is set, and P0IS.HBFS is set, the HBA shall generate an
interrupt.
Bit Reset
Value
0h
0h
0h
Bit Access
RO
RW
RW
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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