EP80579 Datasheet, PDF (1609/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
40.4.1.2
40.4.1.3
40.4.1.4
40.4.1.5
40.4.1.6
Data Size Select (DSS)
The 4-bit data size select (DSS) field is used to select the size of the data transmitted
and received by the SSP. Data can be 4 to 16 bits in length. When data is programmed
to be less than 16 bits, received data is automatically right-justified and the upper bits
in the receive FIFO are zero-filled by receive logic. Transmit data should not be left-
justified by the user before being placed in the transmit FIFO; transmit logic in the SSP
will automatically left-justify the data sample according to the value of DSS before the
sample is transmitted on SSP_TXD. Although it is possible to program data sizes of 1,
2, and 3 bits, these sizes are reserved and produce unpredictable results in the SSP.
When National Microwire frame format is selected, this bit field selects the size of the
received data. Note that the size of the transmitted data is always 8 bits in this mode.
Frame Format (FRF)
The 2-bit frame format (FRF) field is used to select which frame format to use: Motorola
SPI (FRF=00), Texas Instruments synchronous serial (FRF=01), or National Microwire
(FRF=10). Note that FRF=11 is reserved and the SSP will produce unpredictable results
if this value is used.
External Clock Select (ECS)
The external clock select (ECS) bit selects whether the on-chip 3.6864-MHz (2.777MHz
for low-power SKU) clock is used by the SSP or if an off-chip clock is supplied via
SSP_EXTCLK. When ECS=0, the SSP uses the on-chip 3.6864-MHz clock (2.777MHz
for low-power SKU) to produce a range of serial transmission rates. When ECS=1, the
SSP uses SSP_EXTCLK to input a clock supplied from off-chip. The frequency of the
off-chip clock can be any value up to 3.6864 MHz (2.777MHz for low-power SKU). This
off-chip clock is useful when a serial transmission rate, which is not an even multiple of
the internal clock, is required for synchronization with the target off-chip slave device.
Synchronous Serial Port Enable (SSE)
The SSP enable (SSE) bit is used to enable and disable all SSP operations. When
SSE=0, the SSP is disabled; when SSE=1, it is enabled. When the SSP is disabled, all of
its clocks are powered down to minimize power consumption. Note that the SSE is the
only control bit within the SSP that is reset to a known state. It is cleared to zero to
ensure the SSP is disabled following a reset.
When the SSE bit is cleared during active operation, the SSP is disabled immediately,
causing the current frame being transmitted to be terminated. Clearing SSE resets the
SSP’s FIFOs. However the SSP’s control and status registers are not reset. The user
must ensure these registers are properly reconfigured before re-enabling the SSP.
Serial Clock Rate (SCR)
The 8-bit serial clock rate (SCR) bit-field is used to select the baud, or bit rate, of the
SSP. The serial clock generator can be configured to use the internally provided 3.6864-
MHz (2.777MHz for low-power SKU) clock produced by the on-chip PLL or the
externally provided clock. The source clock is divided by a fixed value of 2, and then
divided by the programmable SCR value (0 to 255) plus 1 to generate the serial clock
(SSP_SCLK). When configured to use the internal clock, a total of 256 different bit
rates can be selected. The resultant clock is driven on the SSP_SCLK pin and is used
by the SSP’s transmit logic to drive data on the SSP_TXD pin, and to latch data on the
SSP_RXD pin. Depending on the frame format selected, each transmitted bit is driven
on either the rising or falling edge of SSP_SCLK, and is sampled on the opposite clock
edge.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
1609