EP80579 Datasheet, PDF (975/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
The following bits in I/O space are to be maintained when the CMI enters a low power
state:
Table 25-32. Bits Maintained in Low Power States
Register
Command
Status
Offset
00h
02h
Port Status and Control 10h and 12h
Bit
Description
3 Enter Global Suspend Mode (EGSM)
2 Resume Detect
2 Port Enabled/Disabled
6 Resume Detect
8 Low-speed Device Attached
12 Suspend
When the CMI detects a resume event on any of its ports, it sets the corresponding
USB_STS bit in ACPI space. If USB is enabled as a wake/break event, the system will
wake up and an SCI will be generated.
25.12
USB Legacy Keyboard Operation
When a USB keyboard is plugged into the system, and a standard keyboard is not, the
system may not boot, and DOS legacy software will not run, because the keyboard will
not be identified. The CMI implements a series of trapping operations which will snoop
accesses that go to the keyboard controller, and put the expected data from the USB
keyboard into the keyboard controller.
The following table summarizes the implementation of the bits in the USB Legacy
Keyboard/Mouse Control Registers.
Table 25-33. USB Legacy Keyboard/Mouse Control Register Bit Implementation (Sheet 1 of
2)
Bit #
Bit Name
Summary
15
SMI Caused by End of Pass- Logically 1 bit for all
Through
controllers
13 PCI Interrupt Enable
12
SMI Caused by USB
Interrupt
Independent enable
Independent status
11
SMI Caused by Port 64 Write
Logically 1 bit for all
controllers
10
SMI Caused by Port 64 Read
Logically 1 bit for all
controllers
9
SMI Caused by Port 60 Write
Logically 1 bit for all
controllers
Details
This bit in all host controllers will be set at the same time and
cleared at the same time. It is cleared whenever software
writes a 1 to this bit in any of the classic USB host controllers.
This bit may either be implemented separately for each
controller or shared and aliased.
Each bit provides individual host control
Individual status bits for each controller
This bit in all host controllers will be set at the same time and
cleared at the same time. It is cleared whenever software
writes a 1 to this bit in any of the classic USB host controllers.
This bit may either be implemented separately for each
controller or shared and aliased.
This bit in all host controllers will be set at the same time and
cleared at the same time. It is cleared whenever software
writes a 1 to this bit in any of the classic USB host controllers.
This bit may either be implemented separately for each
controller or shared and aliased.
This bit in all host controllers will be set at the same time and
cleared at the same time. It is cleared whenever software
writes a 1 to this bit in any of the classic USB host controllers.
This bit may either be implemented separately for each
controller or shared and aliased.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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