EP80579 Datasheet, PDF (234/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 7-54. Bus M, Device 1, Function 0: Summary of Gigabit Ethernet Interface Registers
Mapped Through CSRBAR Memory BAR (Sheet 2 of 4)
Offset Start Offset End
Register ID - Description
Default
Value
2C00h
5000h
5200h at 4h
5400h at 8h
5404h at 8h
5600h at 4h
0400h
0410h
0458h
3800h
3804h
3808h
3810h
3818h
3820h
3828h
382Ch
3830h
4000h
4004h
400Ch
4010h
4014h
4018h
401Ch
4020h
4028h
4030h
4034h
403Ch
4040h
4048h
404Ch
4050h
4054h
4058h
405Ch
4060h
4064h
2C03h
5003h
5203h at 4h
5403h at 8h
5407h at 8h
5603h at 4h
0403h
0413h
045Bh
3803h
3807h
380Bh
3813h
381Bh
3823h
382Bh
382Fh
3833h
4003h
4007h
400Fh
4013h
4017h
401Bh
401Fh
4023h
402Bh
4033h
4037h
403Fh
4043h
404Bh
404Fh
4053h
4057h
405Bh
405Fh
4063h
4067h
“RSRPD: Receive Small Packet Detect Interrupt Register” on page 1486
00000000h
“RXCSUM: Receive Checksum Control Register” on page 1487
00000000h
“MTA[0-127] – 128 Multicast Table Array Registers” on page 1488
XXXX_XXXXh
“RAL[0-15] - Receive Address Low Register” on page 1488
XXXXXXXXh
“RAH[0-15] - Receive Address High Register” on page 1489
000XXXXXh
“VFTA[0-127] - 128 VLAN Filter Table Array Registers” on page 1490
XXXXXXXXh
“TCTL: Transmit Control Register” on page 1491
00000008h
“TIPG: Transmit IPG Register” on page 1493
00602008h
“AIT: Adaptive IFS Throttle Register” on page 1495
00000000h
“TDBAL: Transmit Descriptor Base Address Low Register” on page 1496
XXXXXXX0h
“TDBAH: Transmit Descriptor Base Address High Register” on page 1496
XXXXXXXXh
“TDLEN: Transmit Descriptor Length Register” on page 1497
00000000h
“TDH: Transmit Descriptor Head Register” on page 1497
00000000h
“TDT: Transmit Descriptor Tail Register” on page 1498
00000000h
“TIDV: Transmit Interrupt Delay Value Register” on page 1499
00000000h
“TXDCTL: Transmit Descriptor Control Register” on page 1500
00000000h
“TADV: Transmit Absolute Interrupt Delay Value Register” on page 1502
00000000h
“TSPMT: TCP Segmentation Pad And Minimum Threshold Register” on page 1504 01000400h
“CRCERRS: CRC Error Count Register” on page 1505
00000000h
“ALGNERRC: Alignment Error Count Register” on page 1506
00000000h
“RXERRC: Receive Error Count Register” on page 1506
00000000h
“MPC: Missed Packet Count Register” on page 1507
00000000h
“SCC: Single Collision Count Register” on page 1507
0000h
“ECOL: Excessive Collisions Count Register” on page 1508
00000000h
“MCC: Multiple Collision Count Register” on page 1508
00000000h
“LATECOL: Late Collisions Count Register” on page 1509
00000000h
“COLC: Collision Count Register” on page 1509
00000000h
“DC: Defer Count Register” on page 1510
00000000h
“TNCRS: Transmit with No CRS Count Register” on page 1510
00000000h
“CEXTERR: Carrier Extension Error Count Register” on page 1511
00000000h
“RLEC: Receive Length Error Count Register” on page 1511
00000000h
“XONRXC: XON Received Count Register” on page 1512
00000000h
“XONTXC: XON Transmitted Count Register” on page 1512
00000000h
“XOFFRXC: XOFF Received Count Register” on page 1513
00000000h
“XOFFTXC: XOFF Transmitted Count Register” on page 1513
00000000h
“FCRUC: FC Received Unsupported Count Register” on page 1514
00000000h
“PRC64: Good Packets Received Count (64 Bytes) Register” on page 1514
00000000h
“PRC127: Good Packets Received Count (65-127 Bytes) Register” on page 1515 00000000h
“PRC255: Good Packets Received Count (128-255 Bytes) Register” on page 1515 00000000h
Intel^® EP80579 Integrated Processor Product Line Datasheet
234
August 2009
Order Number: 320066-003US