EP80579 Datasheet, PDF (364/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Figure 14-2. FERR/NERR Service Routine
EXIT
If no errors
Error
Irpt/Msg
Read
Global
FERR
else
Read
Global
FERR &
snapshot
always
Clear
Global
FERR
always
Service
Routine
[Global]
Read
Global
NERR &
snapshot
always
If no local errors indicated
NOTE: The local reads must be performed
for the next unit, if any, indicated in the
FERR/NERR snapshot taken
Clear
Global
NERR
always
Clear
Local
NERR
always
Read
Support
Registers
else
if error type has
support registers
Read
Local
NERR
always
always
Read
Local
FERR
elseif
error type has
support registers
else
Read
Support
Registers
always
Clear
Local
FERR
Service
Routine
[Unit]
14.2.1.3
14.2.1.4
FERR/NERR Unit Specific
Each unit has different and specific error bit definitions.
SERR/SMI/SCI Enabling Registers
Each error reported has a full matrix of direction as to what error message it generates.
For each unit FERR/NERR pair there are three more registers that enable each error for
one of the three specific error messages. The logic does not appear to preclude the
generation of all three messages for a single error, but this would not be a
recommended configuration, and this needs to be looked into further. SERR stands for
system error and is for reporting address and data parity errors, or any other
catastrophic system error. SCI stands for system control interrupt and is a shareable
interrupt used to notify the OS of ACPI events. SMI stands for System Management
Interrupt and is an OS-transparent interrupt generated by events on legacy systems.
Intel^® EP80579 Integrated Processor Product Line Datasheet
364
August 2009
Order Number: 320066-003US