EP80579 Datasheet, PDF (751/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
19.2.4.4
Offset 88h: LG2: LPC Generic Decode Range 2 Register
LG2 sets the base address in I/O space for the I/O registers. These registers can be
mapped anywhere in the 64 K I/O space on 16-byte boundaries. The size of this region
can be either 16B, 32B, or 64B based on the setting of ETR3.
Table 19-26. Offset 88h: LG2: LPC Generic Decode Range 2 Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:31:0
Offset Start: 88h
Offset End: 88h
Size: 16 bit
Default: 0000h
Power Well: Core
Bit Range
15 :04
03 :01
00
Bit Acronym
Bit Description
Sticky
BA
Reserved
EN
Base Address: This address is aligned on a 16-byte
boundary, and must have address lines 31:16 as 0.
Note that configuration bits at D31:F0:ACh (bits 13 and
12) allow this range to be increased to 32 or 64 bytes by
forcing matches on address bits 4 and/or 5.
Reserved.
Enable:
0 = Disable
1 = Enables the range specified in BA to be forwarded to
LPC Interface
Bit Reset
Value
0h
0h
0h
Bit Access
RW
RW
19.2.5
19.2.6
19.2.6.1
Power Management Configuration Registers
Offsets A0h – CFh are described in the power management section. Refer to
Chapter 27.0, “Power Management”.
FWH Configuration Registers
Offset D0h: FS1: FWH ID Select 1 Register
This register contains the IDSEL fields the LPC Bridge uses for memory cycles going to
the FWH.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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