EP80579 Datasheet, PDF (1546/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
• Single bit errors will be corrected in all but types 010 and 011, with no error
indication.
• Multiple bit errors will cause a Gbe error response for all other memory types.
• A multiple bit error is caused by forcing multiple mask bits [15:8] and/or multiple
bits of [7:0] for Types 100, 101, 110. Forcing one bit in [15:8] and one bit in [7:0]
will not create a multiple bit error (and will therefore not produce a Gbe Error
response).
Table 37-146.MEM_TST - Memory Error Test Register
Description:
View: PCI 1
BAR: CSRBAR
Bus:Device:Function: M:0:0
Offset Start: 0900h
Offset End: 0903h
View: PCI 2
BAR: CSRBAR
Bus:Device:Function: M:1:0
Offset Start: 0900h
Offset End: 0903h
View: PCI 3
BAR: CSRBAR
Bus:Device:Function: M:2:0
Offset Start: 0900h
Offset End: 0903h
Size: 32 bits
Default: 00000000h
Power
Well:
GbE0: Aux
Gbe1/2: Core
Bit Range
31 : 19
18 : 16
15 : 00
Bit Acronym
Bit Description
Sticky
Rsvd
Select
Mask
Reserved
Selects the memory where the error mask is applied:
000 : None - no errors injected
001 : Statistics Registers
010 : Multicast Filter Memory
011 : Special Packet Filter Memory
100 : TX Descriptor Buffer
101 : RX Descriptor Buffer
110 : Packet Buffer
111 : Flexible Filter Memory
ECC/Parity check bit XOR mask
The Valid Mask bits are selected according to the Select
field, as follows:
001 : 15:8 Reserved; 7:0 ECC Mask
010 : 15:4 Reserved; 3:0 Parity bit Mask
011 : 15:4 Reserved; 3:0 Parity bit Mask
100 : 15:0 ECC Mask
101 : 15:0 ECC Mask
110 : 15:0 ECC Mask
111 : 15:0 Reserved; 3:0 Parity bit Mask
Bit Reset
Value
0h
0h
0h
Bit Access
RV
RW
RW
37.6.8.3
MEM_STS – Memory Error Status Register
This register reports ECC or parity errors, for each of the memories with ECC or parity
coverage. Errors will be reported in this register, regardless of whether they were
induced by the MET logic or through actual hardware errors. Host write DMA
transactions issued after these fatal memory errors are encountered will result in a
data error asserted for every internal bus transaction. CSR target transactions,
including transactions to the errored memory, will complete without error, however the
memory errors will still be logged in the MES register.
If the MEM_ERRH_DIS bit is set (error handling is disabled), the individual memory
errors can be cleared with a write to the appropriate memory error bit in this register,
however the errored memory is likely to produce unexpected GbE functionality.
Intel^® EP80579 Integrated Processor Product Line Datasheet
1546
August 2009
Order Number: 320066-003US