EP80579 Datasheet, PDF (1037/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 26-55. Offset A0h: CNTL_STS - Control/Status Register (Sheet 1 of 2)
Description:
View: PCI
BAR: MBAR
Bus:Device:Function: 0:29:7
Offset Start: A0h
Offset End: A3h
Size: 32 bit
Default: 00000000h
Power Well: Core
Bit Range
31
30
29
28
27
26 :17
16
15 :12
11
10
09 :07
Bit Acronym
Bit Description
Sticky
Reserved Reserved
OWNER_CNT
0 = Ownership of the debug port is NOT forced to the
EHCI controller (Default)
1 = Ownership of the debug port is forced to the EHCI
controller (i.e., immediately taken away from the
companion Classic USB Host controller). If the port
was already owned by the EHCI controller, then
setting this bit has no effect. This bit overrides all of
the ownership-related bits in the standard EHCI
registers.
The value in this bit does not affect the value reported in
the PORTSC Port Owner bit.
Reserved Reserved
0 = Software can clear this by writing a 0 to it. The
hardware clears this bit for the same conditions
where the Port Enable/Disable Change bit (in the
ENABLED_CNT
1=
PORTSC register) is set. (Default)
Debug port is enabled for operation. Software can
directly set this bit if the port is already enabled in
the associated PORTSC register (this is enforced by
the hardware).
Reserved Reserved
Reserved Reserved
DONE_STS
0 = Request Not complete.
1 = Set by hardware to indicate that the request is
complete.
Writing a 1 to this bit will clear it if it is set. Writing a 0 to
this bit has no effect. Reset default = 0.
LINK_ID_STS
This field identifies the link interface. It is hardwired to 0h
to indicate that it is a USB Debug Port.
Reserved Reserved.
IN_USE_CNT
Set by software to indicate that the port is in use. Cleared
by software to indicate that the port is free and may be
used by other software. This bit is cleared after reset.
(This bit has no effect on hardware.)
This field indicates the exception when the
ERROR_GOOD#_STS bit is set. This field must be ignored
if the ERROR_GOOD#_STS bit is 0.
000 No Error.
Note: This must not be seen, since this field must only
be checked if there is an error.
EXCEPTION_ST
S
001 Transaction error: indicates the USB 2.0
transaction had an error (CRC, bad PID,
timeout, etc.)
010 Hardware error. Request was attempted (or in
progress) when port was suspended or reset.
All others are reserved.
Reset default = 000b
Bit Reset
Value
0h
0h
0h
0h
0h
0h
0h
0h
0h
0h
000b
Bit Access
RW
RW
RWC
RO
RW
RO
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
1037