EP80579 Datasheet, PDF (1474/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
37.6.4 Receive Registers: Detailed Descriptions
37.6.4.1
RCTL – Receive Control Register
This register controls the types and sizes of packets received, as well as any
manipulation of those received packets. The size of the receive buffers where those
packets reside before they are transferred to system memory is also controlled here.
Table 37-50. RCTL: Receive Control Register (Sheet 1 of 4)
Description:
View: PCI 1
BAR: CSRBAR
Bus:Device:Function: M:0:0
Offset Start: 0100h
Offset End: 0103h
View: PCI 2
BAR: CSRBAR
Bus:Device:Function: M:1:0
Offset Start: 0100h
Offset End: 0103h
View: PCI 3
BAR: CSRBAR
Bus:Device:Function: M:2:0
Offset Start: 0100h
Offset End: 0103h
Size: 32 bits
Default: 00000000h
GbE0: Aux
Power Well: Gbe1/2:
Core
Bit Range
31 : 27
26
25
24
23
Bit Acronym
Bit Description
Sticky
Rsvd
SECRC
BSEX
Rsvd
PMCF
Reserved
Strip Ethernet CRC. This bit controls whether the
hardware strips the Ethernet CRC from the received
packet. This stripping occurs prior to any checksum
calculations. The stripped CRC is not DMA'd to host
memory and is not included in the length reported in the
descriptor.
Buffer Size Extension. Combined with RCTL.BSIZE to
program the receive buffer size. Control of receive buffer
size permits software to trade-off descriptor performance
versus required storage space. Buffers that are 2048 bytes
require only one descriptor per receive packet maximizing
descriptor efficiency. Buffers that are 256 bytes maximize
memory efficiency at a cost of multiple descriptors for
packets longer than 256 bytes.
RCTL.BSEX = 0 / RCTL.BSIZE = 00 -> Receive Buffer Size
= 2048B
RCTL.BSEX = 0 / RCTL.BSIZE = 01 -> Receive Buffer Size
= 1024B
RCTL.BSEX = 0 / RCTL.BSIZE = 10 -> Receive Buffer Size
= 512B
RCTL.BSEX = 0 / RCTL.BSIZE = 11 -> Receive Buffer Size
= 256B
RCTL.BSEX = 1 / RCTL.BSIZE = 00 -> Reserved
RCTL.BSEX = 1 / RCTL.BSIZE = 01 -> Receive Buffer Size
= 16384B
RCTL.BSEX = 1 / RCTL.BSIZE = 10 -> Receive Buffer Size
= 8192B
RCTL.BSEX = 1 / RCTL.BSIZE = 11 -> Receive Buffer Size
= 4096B
Reserved
Pass MAC Control Frames. This bit controls the DMA
function of MAC control frames (other than flow control). A
MAC control frame in this context must be addressed to
either the MAC control frame multicast address or the
station address, it must match the type field and must NOT
match the PAUSE opcode of 0x0001.
0 = Do not pass MAC control frames
1 = Pass any MAC control frame (type field value of
0x8808) that does not contain the pause opcode of
0x0001.
Bit Reset
Value
0h
0h
0h
0h
0h
Bit Access
RV
RW
RW
RV
RW
Intel^® EP80579 Integrated Processor Product Line Datasheet
1474
August 2009
Order Number: 320066-003US