EP80579 Datasheet, PDF (641/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 16-287.Offset 260h: DDRIOMC0 - DDRIO Mode Register Control Register
Description:
View: PCI
BAR: SMRBASE
Bus:Device:Function: 0:0:0
Offset Start: 260h
Offset End: 263h
Size: 32 bit
Default: 00000078h
Power Well: Core
Bit Range
31 13
12 9
88
Bit Acronym
Bit Description
Sticky
Bit Reset
Value
Bit Access
Reserved Reserved
N
000000000000
0000000b
RO
DQVOXADJ Bits to configure DQ buffer tco balancing
Y
0000b
RW
Combine this bit with DDRVOXCTL0 (defined below)
Encodings:
00 : DQ and CA buffers are in VOX Cross Reference Mode
DDRVOXCTL1
01: Bypass DQ and CA VOX Cross Reference Mode
(default)
Y
0b
RW
10: VOX Bypass Mode
11: Reset VOX Mode
77
Reserved Reserved
N
0b
RO
64
Reserved Reserved
N
111b
RW
This is the least significant bit of DDRVOXCTL. For encoding
33
DDRVOXCTL0 ^{details, see DDRVOXCTL1 above}
Y
1b
RW
20
Reserved Reserved
Y
000b
RW
16.5.1.63 Offset 264h: DDRIOMC1 - DDR IO Mode Control Register 1
This register controls functionality of the DDRIO.
This CSR is in the memory-mapped IO region of Bus 0, Device 0, Function 0 of the
memory controller. The SMRBASE register described in Section 16.1.1.9, “Offset 14h:
SMRBASE - System Memory RCOMP Base Address Register” on page 395, provides the
base address for these registers. The offsets listed for the following registers are
relative to this base address.
The value for BAR for all registers in this section is BAR14h.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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