EP80579 Datasheet, PDF (431/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
16.1.1.42 Offset 64h: DRT1 – DRAM Timing Register 1
This register controls the DRAM timing parameters.
For details about the DRT1 register see “Offset 78h: DRT0 - DRAM Timing Register 0”
on page 424.
Table 16-46. Offset 64h: DRT1 - DRAM timing Register 1 (Sheet 1 of 4)
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:0:0
Offset Start: 64h
Offset End: 67h
Size: 32 bit
Default: 12110000h
Power Well: Core
Bit Range
Bit Acronym
Bit Description
Sticky
(Time for activation / RAS Active Strobe): time to activate
a row of a bank (minimum time bank stays open before it
can be closed/precharged again)
SW needs to program this parameter based on the DDR
speed as shown in the table below.
Note however that the HW will use a different tRAS value
when the DDR commands are generated by the Mbist
Engine. During all other modes the controller will use the
tRAS value programmed in this field.
Bit Reset
Value
Bit Access
DDR
Speed
Encoding
# of CMD
Tras value
clks
used by Mbist
31 :28
tRAS
400
0000
8 (40ns)
12
400
0001
9 (45ns)
12
N
0001b
RW
533
0100
12 (45ns)
12
667
0111
15 (45ns)
15
800
1000
16 (40ns)
18
800
1010
18 (40ns)
18
27 :25
tRTP
RAS to Precharge (needed to calculate Read
AutoPrecharge delay)
Encoding
000
001
010
011
Others
Number of
CMDCLK
delays
2
3
4
5
Reserved
N
001b
RW
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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