EP80579 Datasheet, PDF (1640/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 41-11. Offset 0000h: TS_Control Register
Description:
View: PCI
BAR: CSRBAR
Bus:Device:Function: M:7:0
Offset Start: 00000000h
Offset End: 00000003h
Size: 32 bits
Default: 00000000h
Power Well: Core
Bit Range
2: 2
1: 1
0: 0
Bit Acronym
Bit Description
Sticky
asm
ttm
rst
ASMS Interrupt Mask. Controls whether the indication
that an Auxiliary Slave Mode snapshot, which is the sns bit
in the Time Sync Event register, has been taken should
interrupt the Host processor.
• When this bit is set, the interrupt to the Host is
enabled.
• When cleared, the ASMS interrupt to the Host is
disabled.
Target Time Interrupt Mask. Controls whether the
Target Time interrupt is passed to the Host processor.
• When this bit is set, the interrupt to the Host is
enabled.
• When cleared, the Target Time interrupt to the Host is
disabled.
Reset.
• When a ‘1’ is written to this bit, all logic is returned to
the same default state as when a power-on reset
occurs.
• After writing a ‘1’ to this bit to reset the logic, the
firmware must write a ‘0’ to the bit to indicate the end
of the reset.
Bit Reset
Value
0h
0h
0h
Bit Access
RW
RW
RW
Intel^® EP80579 Integrated Processor Product Line Datasheet
1640
August 2009
Order Number: 320066-003US