EP80579 Datasheet, PDF (1062/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 27-15. Offset 10h: PROC_CNT - Processor Control Register (Sheet 3 of 3)
Description:
View: PCI
BAR: PMBASE (IO)
Bus:Device:Function: 0:31:0
Offset Start: 10h
Offset End: 10h
Size: 32 bit
Default: 00000000h
Power Well: Core
Bit Range
04
Bit Acronym
Bit Description
Sticky
THT_EN
When this bit is set and the system is in a C0 state, it
enables a software controlled STPCLK# throttling. The
duty cycle is selected in the THTL_DTY field.
0 = Disable
1 = Enable
This 3 –bit field determines the duty cycle of the
throttling when the THT_EN bit is set. The duty cycle
indicates the approximate percentage of time the
STPCLK# signal is asserted (low) while in the throttle
mode. The STPCLK# throttle period is 1024 PCICLKs.
Bit Reset
Value
0h
Bit Access
RW
03 : 01
THTL_DTY
PROCHOT_
DTY
Bits[3:0]
000
001
010
011
100
101
110
111
Throttle Mode
Default
(will be 50%)
87.75%
75%
62.5%
50%
37.5%
25%
12.5%
PCI Clocks
(STPCLK#
low)
512
896
768
640
512
384
256
128
000h
RW
00
Reserved Reserved
0h
Intel^® EP80579 Integrated Processor Product Line Datasheet
1062
August 2009
Order Number: 320066-003US