EP80579 Datasheet, PDF (750/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 19-24. Offset 82h: IOE: I/O Enables Register (Sheet 2 of 2)
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:31:0
Offset Start: 82h
Offset End: 83h
Size: 16 bit
Default: 0000h
Power Well: Core
Bit Range
02
01
00
Bit Acronym
Bit Description
Sticky
PPE
CBE
CAE
Parallel Port Enable:
0 = Disable
1 = Enables decoding of the LPT range to LPC. Range is
selected by LIOD.LPT Decode Range Register (D31, F0,
80h, bit 09:08)
Com Port B Enable:
0 = Disable
1 = Enables decoding of the COMB range to LPC. Range is
selected LIOD.CB Decode Range Register (D31, F0, 80h,
bits 06:04)
Com Port A Enable:
0 = Disable
1 = Enables decoding of the COMA range to LPC. Range is
selected LIOD.CA Decode Range Register (D31, F0, 80h,
bits 03:20)
Bit Reset
Value
0h
0h
0h
Bit Access
RW
RW
RW
19.2.4.3
Offset 84h: LG1: LPC Generic Decode Range 1 Register
LG1 sets the base address in I/O space for the I/O registers. These registers can be
mapped anywhere in the 64 K I/O space on 128-byte boundaries.
Table 19-25. Offset 84h: LG1: LPC Generic Decode Range 1 Register
Description:
View: PCI
BAR: Configuration
Bus:Device:Function: 0:31:0
Offset Start: 84h
Offset End: 85h
Size: 16 bit
Default: 0000h
Power Well: Core
Bit Range
15 :07
06 :01
00
Bit Acronym
Bit Description
Sticky
BA
Reserved
EN
Base Address: Base Address for this generic decode
range. This address is aligned on a 128-byte boundary,
and being I/O, must have address lines 31:16 as 0.
This generic decode is for I/O addresses only, not memory
addresses. The size of this range is 128 bytes.
Reserved.
Enable:
0 = Disable
1 = Enables the range specified in BA to be forwarded to
LPC Interface
Bit Reset
Value
0h
0h
0h
Bit Access
RW
RW
Intel^® EP80579 Integrated Processor Product Line Datasheet
750
August 2009
Order Number: 320066-003US