EP80579 Datasheet, PDF (884/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
23.5.10
These bits, when set, affect the legacy IDE ranges 1F0h – 17Fh, 3F6h, 170h – 17Fh,
376h, and the range pointed to by the LBAR register in configuration space. If native
IDE is enabled, trapping will not be performed. If AHCI is enabled, trapping will not be
performed.
LED
The LED must be driven whenever the BSY bit is set in either port. The LED output will
go directly to SATALED#, an active-low open-collector output. When SATALED# is low,
the LED is active. When SATALED# is tri-stated, the LED is inactive.
23.6
AHCI Operation
23.6.1 System Memory Structures
The serial ATA controller supports 2ports, and each port supports 32 commands. The
command list and received FIS may live in 64-bit space
Figure 23-3. Port System Memory Structure
HBA Registers
System Memory
Configuration
Registers
ABAR
Memory Registers
00h
Generic Host
Control
10h
Reserved
100h
Port 0
180h
Port 1
280h
Reserved
3FFh
Command
List
(Port 0)
Received FIS
Structure
(Port 0)
Command
List
(Port 1)
Received FIS
Structure
(Port 1)
Intel^® EP80579 Integrated Processor Product Line Datasheet
884
August 2009
Order Number: 320066-003US