EP80579 Datasheet, PDF (1083/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
27.5.3.3
C2→C0 Break Sequence
CMI returns the processor to a C0 state in order to execute code. This is due to a break
event. See Table 27-28 for the various break event causes.
The following timings are shown in Figure 27-1.
1. A Break event is detected
2. t4a later, CMI sends GO_C0 message to the IMCH.
3. t4b after receiving the Go-C0 message, then IMCH sends an Ack-C0 to the IICH. At
this point, the IMCH is not permitted to send the REQ-C0 (Break Ind) Message.
4. t5 after receiving the Ack-C0 message, CMI deasserts STPCLK# to the processor
(this enables processor instruction stream)
5. The processor is now back in a C0 state
6. t6 after deasserting STPCLK#, CMI unlatches the processor interface signals,
except SMI#, which was not latched for synchronous SMI events. Changed as per
DCN #014, part 4.
27.6
Sleep States
27.6.1
Sleep State Overview
CMI directly supports different sleep states (S1, S3, S4 or S5), which are entered by
setting the SLP_EN bit, or due to a Power Button press. The entry to the Sleep states
are based on several assumptions:
• Entry to a Cx state is mutually exclusive with entry to a Sleep state. This is because
the processor can only perform one register access at a time. A request to Sleep
always has higher priority than throttling.
• Prior to setting the SLP_EN bit, the software turns off processor-controlled
throttling. Thermal throttling cannot be disabled, but setting the SLP_EN bit
disables thermal throttling (since S1, S3, S4 or S5 sleep states have higher
priority).
• The G3 state cannot be entered via any software mechanism. The G3 state
indicates a complete loss of power.
Table 27-30 shows the differences in the sleeping states with regard to the listed
output signals:
27.6.2 Initiating Sleep States
Table 27-30. Sleep State Output Conditions
State
S1
S3
S4
S5
STPCLK#
Active
Active
Active
Active
CPUSLP#
Optionally
Active
Plane off
Plane off
Plane off
SLP_S3#
Inactive
Active
Active
Active
SLP_S4#
Inactive
Inactive
Active
Active
SLP_S5#
Inactive
Inactive
Inactive
Active
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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