EP80579 Datasheet, PDF (719/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 18-6. Offset 06h: TSTS2 - TCO 2 STS Register (Sheet 2 of 2)
Description:
View: PCI
BAR: TCOBASE (IO)
Bus:Device:Function: 0:31:0
Offset Start: 06h
Offset End: 07h
Size: 16 bit
Default: 0000h
Power Well: Resume
Bit Range
02
01
00
Bit Acronym
Bit Description
Sticky
DOACPU_
STS
SECOND_
TO_STS
INTRD_DET
0 = Cleared based on RSMRST# or by software writing
a 1 to this bit. Software must first clear the
SECOND_TO_STS bit before writing a 1 to clear the
BOOT_STS bit.
1 = Set to 1 when the SECOND_TO_STS bit goes from
0 to 1 and the processor has not fetched the first
instruction.
If rebooting due to a SECOND_TO_STS bit set (= 1) and
the DOACPU_STS bit is:
0 = The BIOS can conclude that the system rebooted
due to some lockup (such as on NSI), but not due
to a processor booting issue.
1 = Reboots using the ‘safe’ multiplier (1111). This
allows the system to recover from a processor
frequency multiplier that is too high, and allows the
BIOS to check the DOACPU_STS bit at boot. If the
bit is set and the frequency multiplier is 1111, then
the BIOS knows that the processor has been
programmed to an illegal multiplier.
Note: Software must clear the SECOND_TO_STS bit
first, then the DOACPU_STS bit (use two
separate I/O write operations).
0 = Software clears this bit by writing a 1 to it or by a
RSMRST#.
1 = Sets this bit to 1 to indicate that the TIMEOUT bit
had been (or is currently) set and a second timeout
occurred before the TCO_RLD register was written.
If this bit is set and the NO_REBOOT configuration
bit is 0, then reboots the system after the second
timeout. The reboot is done by asserting PLTRST#.
Intruder Detect. This bit resides in the RTC well.
0 = Software clears this bit by writing a 1 to this bit or
by RTEST#.
1 = Set to indicate that an intrusion was detected. This
bit is latched. The INTRUDER# signal must be
asserted for a minimum of 1 ms to guarantee that
the INTRD_DET bit is set.
This bit has a recovery time. After writing a 1 to this bit
position (to clear it), the bit may be read back as a 1 for
up 65 µs before it is read as a 0. Software must be
aware of this recovery time when reading this bit after
clearing it.
If the INTRUDER# signal is active when the software
attempts to clear the INTRD_DET bit, the bit remains
one, and the SMI# is generated again immediately. The
SMI handler can clear the INTRD_SEL bits (TCOBASE +
0Ah, bits 2:1) to avoid further SMIs. However, if the
INTRUDER# signals goes inactive and then active again,
there is not further SMIs (because the INTRD_SEL bits
would select that no SMI# be generated).
If the INTRUDER# signal goes inactive some point after
the INTRD_DET bit is written as a 1, then the
INTRD_DET signal goes to a 0 when INTRUDER# input
signal goes inactive. This is slightly different than a
classic sticky bit, since most sticky bits would remain
active indefinitely when the signal goes active and
would immediately go inactive when a 1 is written to the
bit.
Bit Reset
Value
0h
0h
0h
Bit Access
RWC
RWC
RWC
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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