EP80579 Datasheet, PDF (1557/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
37.7.4.6 Timing Guarantees
The GbE guarantees the following start-up or power state transition related timing
parameters.
Table 37-149.GbE Timing Guarantees
Parame
ter
Description
tpgee
tpree
PWR_OK assertion to start of
EEPROM read.
RESET deassertion to start of
EEPROM read
tee
EEPROM read duration
td3ps
D3 write to power reduction.
Min
Max.
Notes
0
0
24µs
0
1µs
10µs
10ms
500ns
The MAC must attempt to read
the EEPROM to determine if an
EEPROM is present, so this
applies even if no EEPROM is
connected.
37.7.5
Power Management Extended Capabilities Registers
Power Management registers are part of the capabilities linked list pointed to by the
Capabilities Pointer (Cap_Ptr) in the PCI configuration space.
All fields are reset by PWR_GOOD. All of the fields except PME_En and PME_Status are
reset by the deassertion (rising edge) of UNIT_RESET. If AUX_PWR_PRESENT=0, the
PME_En and PME_Status fields also reset by the deassertion (rising edge) of
UNIT_RESET.
Refer to Section 35.6.1.17, “Offset DCh: PCID – Power Management Capability ID
Register” on page 1251, Section 35.6.1.18, “Offset DDh: PCP – Power Management
Next Capability Pointer Register” on page 1251, Section 35.6.1.19, “Offset DEh: PMCAP
– Power Management Capability Register” on page 1252, and Section 35.6.1.20,
“Offset E0h: PMCS – Power Management Control and Status Register” on page 1253 for
register details.
§§
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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