EP80579 Datasheet, PDF (659/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
16.6.1.6
Note:
Offset 14h: SUAR0 - Channel 0 Source Upper Address Register
The upper address will not be used in the EP80579, which is limited to 32bit addressing
The Source Upper Address Register (SUAR) contains the upper 32-bit source address
for the current DMA transfer. This register is loaded by the IMCH when the source upper
address field of a new chain descriptor is read.
Because the EP80579 supports 32 bit addressing only, this register needs to be set to
“0” at all times.
Table 16-302.Offset 14h: SUAR0 - Channel 0 Source Upper Address Register
Description:
View: PCI
BAR: EDMALBAR
Bus:Device:Function: 0:1:0
Offset Start: 14h
Offset End: 17h
Size: 32 bit
Default: 00000000h
Power Well: Core
Bit Range
31 : 00
Bit Acronym
Bit Description
SUAR0
Current Source Address: The upper 32-bit source
memory address for the current DMA transfer.
Sticky
Bit Reset
Value
0000000h
Bit Access
RO
16.6.1.7
Offset 18h: DAR0 - Channel 0 Destination Address Register
The Destination Address Register (DAR) contains the lower 32-bit destination address
for the current DMA transfer. This register is loaded by the IMCH when the destination
address field of a new chain descriptor is read.
Table 16-303.Offset 18h: DAR0 - Channel 0 Destination Address Register
Description:
View: PCI
BAR: EDMALBAR
Bus:Device:Function: 0:1:0
Offset Start: 18h
Offset End: 1Bh
Size: 32 bit
Default: 00000000h
Power Well: Core
Bit Range
31 : 00
Bit Acronym
Bit Description
DAR0
Current Destination Address: The lower 32-bit
destination memory address for the current DMA
transfer.
Sticky
Bit Reset
Value
Bit Access
0000000h
RO
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
659