EP80579 Datasheet, PDF (1097/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
28.0 IA-32 Core Interface
28.1
IA-32 Core Interface I/O-Mapped Register Details
Table 28-1. IA-32 Core Interface Signal State
Signal Name
S3 Hot
S3 Cold
S5
A20M#
CPUSLP#
IGNNE#
INIT#
INTR
Low
Low
Low
Low
Low
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
NMI
Low
Off
Off
SMI#
Low
Off
Off
STPCLK#
Low
Off
Off
FERR#
X
Low
Low
Notes:
X = Don’t care
ND = Not Determined. May be high or low depending on programming.
Table 28-2. Summary of IA-32 Core Interface Registers Mapped in I/O Space
Offset Start Offset End
Register ID - Description
61h
70h
92h
F0h
CF9h
61h
70h
92h
F0h
CF9h
“Offset 61h: NMI_STS_CNT - NMI Status and Control Register” on page 1098
“Offset 70h: NMI_EN - NMI Enable (and Real Time Clock Index) Register” on
page 1099
“Offset 92h: PORT92 - Fast A20 and Init Register” on page 1100
“Offset F0h: COPROC_ERR - Coprocessor Error Register” on page 1100
“Offset CF9h: RST_CNT - Reset Control Register” on page 1101
Default
Value
00h
80h
00h
00h
00h
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
1097