EP80579 Datasheet, PDF (1159/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
32.2.1.5
Offset 100h: HPTCC[0-2] - Timer n Configuration and
Capabilities Register
General Behavioral Rules:
• Software can access the various bytes in this register using 32-bit or 64-bit
accesses.
• 32-bit accesses can be done to offset 1x0h or 1x4h. 64-bit accesses can be done to
1x0h.
• 32-bit accesses must not be done to 1x1h, 1x2h, 1x3h, 1x5h, 1x6h, 1x7h.
Note:
The letter n can be 0, 1 or 2, referring to Timer 0, 1 or 2.
Table 32-6. Offset 100h: HPTCC[0-2] - Timer n Configuration and Capabilities Register
(Sheet 1 of 3)
Description:
Timer 0:
+ 107h
100 – 107h, Timer 1:
120 – 127h, Timer 2:
140 – 147h, Timer n:
(20h * n) +100h
-
(20h * n)
View: IA F
Base Address: HPTC
Offset Start: 100h at 20h
Offset End: 107h at 20h
Size: 64 bit
Default: Xh
Power Well: Core
Bit Range Bit Acronym
Bit Description
Sticky
Bit Reset
Value
Bit Access
63 :56
55 :52
Reserved Reserved: These bits return 0 when read.
Timer Interrupt Route Capability:
Timer 0, 1:Bits 52, 53, 54, and 55 in this field
(corresponding to IRQ 20, 21, 22, and 23) have a value of
1. Writes will have no effect.
Timer 2:Bits 43, 52, 53, 54, and 55 in this field
TIMERn_INT_R _{(corresponding to IRQ 11, 20, 21, 22, and 23) have a}
OUT_CAP value of 1. Writes will have no effect.
0h
RO
X
RO
51 :44
43
If IRQ 11 is used for High Precision Event Timer #2,
software must ensure IRQ 11 is not shared with any other
devices to guarantee the proper operation of High
Precision Event Timer #2.
Reserved Reserved: These bits return 0 when read.
Timer Interrupt Route Capability:
Timer 0, 1:Bits 52, 53, 54, and 55 in this field
(corresponding to IRQ 20, 21, 22, and 23) have a value of
1. Writes will have no effect.
Timer 2:Bits 43, 52, 53, 54, and 55 in this field
TIMERn_INT_R _{(corresponding to IRQ 11, 20, 21, 22, and 23) have a}
OUT_CAP value of 1. Writes will have no effect.
0h
RO
X
RO
If IRQ 11 is used for High Precision Event Timer #2,
software must ensure IRQ 11 is not shared with any other
devices to guarantee the proper operation of High
Precision Event Timer #2.
42 :14
Reserved Reserved: These bits return 0 when read.
0h
RO
Note: Reads or writes to unimplemented timers must not be attempted. Reads from any unimplemented registers return an
undetermined value.
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
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