EP80579 Datasheet, PDF (1019/1916 Pages) Intel Corporation – Intel® EP80579 Integrated Processor Product Line

Intel^® EP80579 Integrated Processor
Table 26-48. Offset 64h: PORTSC - Port N Status and Control Register (Sheet 4 of 5)
Description: Port 1 64 - 67h, Port 2 68 - 6Bh
View: PCI
BAR: MBAR
Bus:Device:Function: 0:29:7
Offset Start: 64h
Offset End: 67h
View: PCI
BAR: MBAR
Bus:Device:Function: 0:29:7
Offset Start: 68h
Offset End: 6Bh
Size: 32 bit
Default: 00003000h
Power Well: Suspend
Bit Range
07
06
05
Bit
Acronym
Bit Description
Sticky
PS
FPR
OCC
Suspend:
0 = Port not in suspend state (default).
1 = Port in suspend state.
Port Enabled Bit and Suspend bit of this register define the
port states as follows:
Bits [Port Enabled, Suspend]Port State
0X
Disable
10
Enable
11
Suspend
When in suspend state, downstream propagation of data is
blocked on this port, except for port reset. The blocking
occurs at the end of the current transaction, if a transaction
was in progress when this bit was written to a 1. In the
suspend state, the port is sensitive to resume detection. The
bit status does not change until the port is suspended and
there may be a delay in suspending a port if there is a
transaction currently in progress on the USB.
A write of zero to this bit is ignored by the host controller. The
host controller will unconditionally set this bit to a zero when:
• Software sets the Force Port Resume bit to a zero (from a
one).
• Software sets the Port Reset bit to a one (from a zero).
If host software sets this bit to a one when the port is not
enabled (i.e., Port enabled bit is a zero) the results are
undefined.
Force Port Resume:
0 = No resume (K-state) detected/driven on port (default).
1 = Resume detected/driven on port.
This functionality defined for manipulating this bit depends on
the value of the Suspend bit. For example, if the port is not
suspended (Suspend and Enabled bits are a one) and
software transitions this bit to a one, then the effects on the
bus are undefined.
Software sets this bit to a 1 to drive resume signaling. The
Host Controller sets this bit to a 1 if a J-to-K transition is
detected while the port is in the Suspend state. When this bit
transitions to a one because a J-to-K transition is detected,
the Port Change Detect bit in the USBSTS register is also set
to a one. If software sets this bit to a one, the host controller
must not set the Port Change Detect bit.
When the EHCI controller owns the port, the resume
sequence follows the defined sequence documented in the
USB Rev. 2.0 Specification. The resume signaling (Full-speed
'K') is driven on the port as long as this bit remains a one.
Software must appropriately time the Resume and set this bit
to a zero when the appropriate amount of time has elapsed.
Writing a zero (from one) causes the port to return to high-
speed mode (forcing the bus below the port into a high-speed
idle). This bit will remain a one until the port has switched to
the high-speed idle. The host controller must complete this
transition within 2 milliseconds of software setting this bit to
a zero.
Overcurrent Change:
0 = No change (default).
1 = This bit gets set to a one when there is a change to the
Overcurrent Active bit. Software clears this bit by writing
a one to this bit position. The functionality of this bit is
not dependent upon the port owner.
Bit Reset
Value
0h
0h
0h
Bit Access
RW
RW
RWC
August 2009
Order Number: 320066-003US
Intel^® EP80579 Integrated Processor Product Line Datasheet
1019